Add explicit pinctrl configuration for UART0 Signed-off-by: Sjoerd Simons --- V1 -> V2: Move pinctrl to the soc dtsi as it's the only available pinmux for the uart. And very rare for the pins to be used for anything else. --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 58c99f2a25218..4fa35bbf0a9cd 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -102,6 +102,8 @@ uart0: serial@11002000 { clocks = <&infracfg CLK_INFRA_UART0_SEL>, <&infracfg CLK_INFRA_UART0_CK>; clock-names = "baud", "bus"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; status = "disabled"; }; @@ -229,6 +231,13 @@ pio: pinctrl@11d00000 { gpio-controller; #gpio-cells = <2>; #interrupt-cells = <2>; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; }; efuse@11f20000 { -- 2.51.0 Add memory range handled by ARM Trusted Firmware Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Sjoerd Simons --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 4fa35bbf0a9cd..130ce2fda3995 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -41,6 +41,18 @@ psci { method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; + no-map; + }; + }; + soc { compatible = "simple-bus"; ranges; -- 2.51.0 This hardware block amongst other things includes a multiplexer for a high-speed Combo-Phy. This binding allows exposing the multiplexer Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Sjoerd Simons --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 657c38175fba2..51511078c4c3b 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -193,6 +193,7 @@ properties: - mediatek,mt2701-pctl-a-syscfg - mediatek,mt2712-pctl-a-syscfg - mediatek,mt6397-pctl-pmic-syscfg + - mediatek,mt7981-topmisc - mediatek,mt7988-topmisc - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg -- 2.51.0 Add compatible string for MediaTek MT7981 PCIe Gen3 controller. The MT7981 PCIe controller is compatible with the MT8192 PCIe controller. Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Sjoerd Simons --- V1 -> V2: Improve commit subject --- Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index 0278845701ce8..4db700fc36ba7 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -48,6 +48,7 @@ properties: oneOf: - items: - enum: + - mediatek,mt7981-pcie - mediatek,mt7986-pcie - mediatek,mt8188-pcie - mediatek,mt8195-pcie -- 2.51.0 Add a compatible string for Filogic 820, this chip integrates a MediaTek generic T-PHY version 2 Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Sjoerd Simons --- Documentation/devicetree/bindings/phy/mediatek,tphy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index b2218c1519391..ff5c77ef11765 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -80,6 +80,7 @@ properties: - mediatek,mt2712-tphy - mediatek,mt6893-tphy - mediatek,mt7629-tphy + - mediatek,mt7981-tphy - mediatek,mt7986-tphy - mediatek,mt8183-tphy - mediatek,mt8186-tphy -- 2.51.0 Add device tree nodes for PCIe controller and USB3 XHCI host controller on MT7981B SoC. Both controllers share the USB3 PHY which can be configured for either USB3 or PCIe operation. The USB3 XHCI controller supports USB 2.0 and USB 3.0 SuperSpeed operation. The PCIe controller is compatible with PCIe Gen2 specifications. Also add the topmisc syscon node required for USB/PCIe PHY multiplexing. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Sjoerd Simons --- V1 -> V2: Keep xhci reg and phys properties in single lines --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 80 +++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 130ce2fda3995..fab22cbbece47 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -2,6 +2,7 @@ #include #include +#include #include / { @@ -223,6 +224,55 @@ auxadc: adc@1100d000 { status = "disabled"; }; + xhci: usb@11200000 { + compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, + <&infracfg CLK_INFRA_IUSB_CK>, + <&infracfg CLK_INFRA_IUSB_133_CK>, + <&infracfg CLK_INFRA_IUSB_66M_CK>, + <&topckgen CLK_TOP_U2U3_XHCI_SEL>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + status = "disabled"; + }; + + pcie: pcie@11280000 { + compatible = "mediatek,mt7981-pcie", + "mediatek,mt8192-pcie"; + reg = <0 0x11280000 0 0x4000>; + reg-names = "pcie-mac"; + ranges = <0x82000000 0 0x20000000 + 0x0 0x20000000 0 0x10000000>; + bus-range = <0x00 0xff>; + clocks = <&infracfg CLK_INFRA_IPCIE_CK>, + <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, + <&infracfg CLK_INFRA_IPCIER_CK>, + <&infracfg CLK_INFRA_IPCIEB_CK>; + clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; + device_type = "pci"; + phys = <&u3port0 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + interrupts = ; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + status = "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + pio: pinctrl@11d00000 { compatible = "mediatek,mt7981-pinctrl"; reg = <0 0x11d00000 0 0x1000>, @@ -252,6 +302,36 @@ mux { }; }; + topmisc: topmisc@11d10000 { + compatible = "mediatek,mt7981-topmisc", "syscon"; + reg = <0 0x11d10000 0 0x10000>; + #clock-cells = <1>; + }; + + usb_phy: t-phy@11e10000 { + compatible = "mediatek,mt7981-tphy", + "mediatek,generic-tphy-v2"; + ranges = <0 0 0x11e10000 0x1700>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x900>; + clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,syscon-type = <&topmisc 0x218 0>; + }; + }; + efuse@11f20000 { compatible = "mediatek,mt7981-efuse", "mediatek,efuse"; reg = <0 0x11f20000 0 0x1000>; -- 2.51.0 Enable the PCIe controller and USB3 XHCI host on the OpenWrt One board. The USB controller is configured for USB 2.0 only mode, as the shared USB3/PCIe PHY is dedicated to PCIe functionality on this board. Signed-off-by: Sjoerd Simons --- .../boot/dts/mediatek/mt7981b-openwrt-one.dts | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts index 968b91f55bb27..5834273839c17 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -20,8 +20,53 @@ memory@40000000 { reg = <0 0x40000000 0 0x40000000>; device_type = "memory"; }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pio { + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_pereset"; + }; + }; }; &uart0 { status = "okay"; }; + +&usb_phy { + status = "okay"; +}; + +&xhci { + phys = <&u2port0 PHY_TYPE_USB2>; + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + mediatek,u3p-dis-msk = <0x01>; + status = "okay"; +}; -- 2.51.0 Different SoCs have different numbers of Wireless Ethernet Dispatch (WED) units: - MT7981: Has 1 WED unit - MT7986: Has 2 WED units - MT7988: Has 2 WED units Update the binding to reflect these hardware differences. The MT7981 also uses infracfg for PHY switching, so allow that property. Signed-off-by: Sjoerd Simons --- V1 -> V2: Only overwrite constraints that are different from the default --- Documentation/devicetree/bindings/net/mediatek,net.yaml | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml index b45f67f92e80d..04224e0ff408e 100644 --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml @@ -112,7 +112,7 @@ properties: mediatek,wed: $ref: /schemas/types.yaml#/definitions/phandle-array - minItems: 2 + minItems: 1 maxItems: 2 items: maxItems: 1 @@ -338,12 +338,13 @@ allOf: - const: netsys0 - const: netsys1 - mediatek,infracfg: false - mediatek,sgmiisys: minItems: 2 maxItems: 2 + mediatek,wed: + maxItems: 1 + - if: properties: compatible: @@ -385,6 +386,9 @@ allOf: minItems: 2 maxItems: 2 + mediatek,wed: + minItems: 2 + - if: properties: compatible: @@ -429,6 +433,9 @@ allOf: - const: xgp2 - const: xgp3 + mediatek,wed: + minItems: 2 + patternProperties: "^mac@[0-2]$": type: object -- 2.51.0 Add device tree nodes for the Ethernet subsystem on MT7981B SoC, including: - Ethernet MAC controller with dual GMAC support - Wireless Ethernet Dispatch (WED) - SGMII PHY controllers for high-speed Ethernet interfaces - Reserved memory regions for WiFi offload processor Signed-off-by: Sjoerd Simons --- V1 -> V2: Don't add unneeded interrupt-parent --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 133 +++++++++++++++++++++++++++++- 1 file changed, 132 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index fab22cbbece47..3510a26cb5112 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -2,6 +2,7 @@ #include #include +#include #include #include @@ -47,11 +48,36 @@ reserved-memory { #size-cells = <2>; ranges; + wo_boot: wo-boot@15194000 { + reg = <0 0x15194000 0 0x1000>; + no-map; + }; + + wo_ilm0: wo-ilm@151e0000 { + reg = <0 0x151e0000 0 0x8000>; + no-map; + }; + + wo_dlm0: wo-dlm@151e8000 { + reg = <0 0x151e8000 0 0x2000>; + no-map; + }; + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ secmon_reserved: secmon@43000000 { reg = <0 0x43000000 0 0x30000>; no-map; }; + + wo_emi0: wo-emi@47d80000 { + reg = <0 0x47d80000 0 0x40000>; + no-map; + }; + + wo_data: wo-data@47dc0000 { + reg = <0 0x47dc0000 0 0x240000>; + no-map; + }; }; soc { @@ -107,6 +133,18 @@ pwm@10048000 { #pwm-cells = <2>; }; + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7981-sgmiisys_0", "syscon"; + reg = <0 0x10060000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7981-sgmiisys_1", "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + uart0: serial@11002000 { compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x100>; @@ -345,15 +383,108 @@ soc-uuid@140 { thermal_calibration: thermal-calib@274 { reg = <0x274 0xc>; }; + + phy_calibration: phy-calib@8dc { + reg = <0x8dc 0x10>; + }; }; - clock-controller@15000000 { + ethsys: clock-controller@15000000 { compatible = "mediatek,mt7981-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; + wed: wed@15010000 { + compatible = "mediatek,mt7981-wed", + "syscon"; + reg = <0 0x15010000 0 0x1000>; + interrupts = ; + memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, + <&wo_data>, <&wo_boot>; + memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", + "wo-data", "wo-boot"; + mediatek,wo-ccif = <&wo_ccif0>; + }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7981-eth"; + reg = <0 0x15100000 0 0x40000>; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_SGM_325M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>, + <&topckgen CLK_TOP_CB_SGM_325M>; + clocks = <ðsys CLK_ETH_FE_EN>, + <ðsys CLK_ETH_GP2_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_WOCPU0_EN>, + <&topckgen CLK_TOP_SGM_REG>, + <&sgmiisys0 CLK_SGM0_TX_EN>, + <&sgmiisys0 CLK_SGM0_RX_EN>, + <&sgmiisys0 CLK_SGM0_CK0_EN>, + <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, + <&sgmiisys1 CLK_SGM1_TX_EN>, + <&sgmiisys1 CLK_SGM1_RX_EN>, + <&sgmiisys1 CLK_SGM1_CK1_EN>, + <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>; + clock-names = "fe", "gp2", "gp1", "wocpu0", + "sgmii_ck", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", + "sgmii2_tx250m", "sgmii2_rx250m", + "sgmii2_cdr_ref", "sgmii2_cdr_fb", + "netsys0", "netsys1"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0", + "pdma1", "pdma2", "pdma3"; + sram = <ð_sram>; + #address-cells = <1>; + #size-cells = <0>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; + mediatek,infracfg = <&topmisc>; + mediatek,wed = <&wed>; + status = "disabled"; + + mdio_bus: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + int_gbe_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + phy-mode = "gmii"; + phy-is-integrated; + nvmem-cells = <&phy_calibration>; + nvmem-cell-names = "phy-cal-data"; + }; + }; + }; + + eth_sram: sram@15140000 { + compatible = "mmio-sram"; + reg = <0 0x15140000 0 0x40000>; + ranges = <0 0x15140000 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + wo_ccif0: syscon@151a5000 { + compatible = "mediatek,mt7986-wo-ccif", "syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupts = ; + }; + wifi@18000000 { compatible = "mediatek,mt7981-wmac"; reg = <0 0x18000000 0 0x1000000>, -- 2.51.0 The openwrt one has a SPI NOR flash which from factory is used for: * Recovery system * WiFi eeprom data * ethernet Mac addresses Describe this following the same partitions as the openwrt configuration uses. Signed-off-by: Sjoerd Simons --- V1 -> V2: - Use numeric drive-strength values rather then defines - Make nvmem cell labers more meaningfull - Only define nvmem cells used in later patches by devicetree --- .../boot/dts/mediatek/mt7981b-openwrt-one.dts | 77 ++++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 2 +- 2 files changed, 78 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts index 5834273839c17..183e48d985ed7 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -3,6 +3,7 @@ /dts-v1/; #include "mt7981b.dtsi" +#include "dt-bindings/pinctrl/mt65xx.h" / { compatible = "openwrt,one", "mediatek,mt7981b"; @@ -53,6 +54,82 @@ mux { groups = "pcie_pereset"; }; }; + + spi2_flash_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2"; + }; + + conf-pu { + bias-pull-up = ; + drive-strength = <8>; + pins = "SPI2_CS", "SPI2_WP"; + }; + + conf-pd { + bias-pull-down = ; + drive-strength = <8>; + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + }; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + #address-cells = <1>; + #size-cells = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x00000 0x40000>; + label = "bl2-nor"; + }; + + partition@40000 { + reg = <0x40000 0xc0000>; + label = "factory"; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + wifi_factory_calibration: eeprom@0 { + reg = <0x0 0x1000>; + }; + + wan_factory_mac: macaddr@24 { + reg = <0x24 0x6>; + compatible = "mac-base"; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@100000 { + reg = <0x100000 0x80000>; + label = "fip-nor"; + }; + + partition@180000 { + reg = <0x180000 0xc80000>; + label = "recovery"; + }; + }; + }; }; &uart0 { diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 3510a26cb5112..2c9819f28fdc2 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -195,7 +195,7 @@ i2c@11007000 { status = "disabled"; }; - spi@11009000 { + spi2: spi@11009000 { compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; reg = <0 0x11009000 0 0x1000>; interrupts = ; -- 2.51.0 Enable the Ethernet subsystem on OpenWrt One board with dual-MAC configuration: - GMAC0: Connected to external Airoha EN8811H 2.5GbE PHY via SGMII (2500base-x mode) for WAN connectivity with LED indicators - GMAC1: Connected to internal MT7981 1GbE PHY (GMII mode) for LAN Ethernet aliases are defined to provide consistent network interface naming (ethernet0 = LAN, ethernet1 = WAN). Signed-off-by: Sjoerd Simons --- V1 -> V2: - Switch gmac0 phy irq to Level - Update mac nvmem label name --- .../boot/dts/mediatek/mt7981b-openwrt-one.dts | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts index 183e48d985ed7..90edb9f493c6d 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -3,6 +3,8 @@ /dts-v1/; #include "mt7981b.dtsi" +#include +#include #include "dt-bindings/pinctrl/mt65xx.h" / { @@ -10,6 +12,8 @@ / { model = "OpenWrt One"; aliases { + ethernet0 = &gmac1; + ethernet1 = &gmac0; serial0 = &uart0; }; @@ -41,6 +45,58 @@ reg_5v: regulator-5v { }; }; +ð { + status = "okay"; + + /* WAN interface */ + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + nvmem-cells = <&wan_factory_mac 0>; + nvmem-cell-names = "mac-address"; + phy-mode = "2500base-x"; + phy-handle = <&phy15>; + }; + + /* LAN interface */ + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + }; +}; + +&mdio_bus { + phy15: ethernet-phy@f { + compatible = "ethernet-phy-id03a2.a411"; + reg = <0xf>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + airoha,pnswap-rx; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + function = LED_FUNCTION_WAN; + color = ; + }; + + led@1 { + reg = <1>; + function = LED_FUNCTION_WAN; + color = ; + }; + }; + }; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; @@ -132,6 +188,10 @@ partition@180000 { }; }; +&sgmiisys0 { + mediatek,pnswap; +}; + &uart0 { status = "okay"; }; -- 2.51.0 Disable the wifi block by default as it won't function properly without at least pin muxing. This doesn't enable wifi on any of the existing mt7981b devices as a required memory-region property is missing, causing the driver to fail probing anyway. Signed-off-by: Sjoerd Simons --- V2: Newly introduced patch --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 2c9819f28fdc2..065f5a3c8b26a 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -499,6 +499,7 @@ wifi@18000000 { clock-names = "mcu", "ap2conn"; resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; reset-names = "consys"; + status = "disabled"; }; }; -- 2.51.0 Add required memory region for the builtin wifi block. Signed-off-by: Sjoerd Simons --- V1 -> V2: Don't set status to in this patch --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 065f5a3c8b26a..eb2effb3c1ed2 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -69,6 +69,11 @@ secmon_reserved: secmon@43000000 { no-map; }; + wmcpu_emi: wmcpu-reserved@47c80000 { + reg = <0 0x47c80000 0 0x100000>; + no-map; + }; + wo_emi0: wo-emi@47d80000 { reg = <0 0x47d80000 0 0x40000>; no-map; @@ -497,6 +502,7 @@ wifi@18000000 { clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; clock-names = "mcu", "ap2conn"; + memory-region = <&wmcpu_emi>; resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; reset-names = "consys"; status = "disabled"; -- 2.51.0 Enable Dual-band WiFI 6 functionality on the Openwrt One Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Sjoerd Simons --- V1 -> V2: Update eeprom node label --- .../boot/dts/mediatek/mt7981b-openwrt-one.dts | 24 ++++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 2 +- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts index 90edb9f493c6d..b13f16d7816bf 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -129,6 +129,22 @@ conf-pd { pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; }; }; + + wifi_dbdc_pins: wifi-dbdc-pins { + mux { + function = "eth"; + groups = "wf0_mode1"; + }; + + conf { + pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4", + "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6", + "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10", + "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ", + "WF_CBA_RESETB", "WF_DIG_RESETB"; + drive-strength = ; + }; + }; }; &spi2 { @@ -200,6 +216,14 @@ &usb_phy { status = "okay"; }; +&wifi { + nvmem-cells = <&wifi_factory_calibration>; + nvmem-cell-names = "eeprom"; + pinctrl-names = "dbdc"; + pinctrl-0 = <&wifi_dbdc_pins>; + status = "okay"; +}; + &xhci { phys = <&u2port0 PHY_TYPE_USB2>; vusb33-supply = <®_3p3v>; diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index eb2effb3c1ed2..17dd13d4c0015 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -490,7 +490,7 @@ wo_ccif0: syscon@151a5000 { interrupts = ; }; - wifi@18000000 { + wifi: wifi@18000000 { compatible = "mediatek,mt7981-wmac"; reg = <0 0x18000000 0 0x1000000>, <0 0x10003000 0 0x1000>, -- 2.51.0 The openwrt has 3 status leds at the front: * red: Used as failsafe led by openwrt * white: Used as boot led by openwrt * green: Used as running/upgrade led by openwrt On the back each RJ45 jack has the typical amber/green leds. For the WAN jack this is hardware controlled by the phy, for LAN these are under software control and enabled by this patch. Signed-off-by: Sjoerd Simons --- V1 -> V2: - Improve commit message - Re-order nodes to be alphabetical --- .../boot/dts/mediatek/mt7981b-openwrt-one.dts | 57 ++++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 2 +- 2 files changed, 58 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts index b13f16d7816bf..b308b7ad4945d 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -26,6 +26,50 @@ memory@40000000 { device_type = "memory"; }; + pwm-leds { + compatible = "pwm-leds"; + + led-0 { + color = ; + default-brightness = <0>; + function = LED_FUNCTION_STATUS; + max-brightness = <255>; + pwms = <&pwm 0 10000>; + }; + + led-1 { + color = ; + default-brightness = <0>; + function = LED_FUNCTION_STATUS; + max-brightness = <255>; + pwms = <&pwm 1 10000>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 9 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&pio 34 GPIO_ACTIVE_LOW>; + linux,default-trigger = "netdev"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&pio 35 GPIO_ACTIVE_LOW>; + linux,default-trigger = "netdev"; + }; + }; + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; @@ -111,6 +155,13 @@ mux { }; }; + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0_0", "pwm1_1"; + }; + }; + spi2_flash_pins: spi2-pins { mux { function = "spi"; @@ -147,6 +198,12 @@ conf { }; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &spi2 { pinctrl-names = "default"; pinctrl-0 = <&spi2_flash_pins>; diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 17dd13d4c0015..66d89495bac52 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -126,7 +126,7 @@ apmixedsys: clock-controller@1001e000 { #clock-cells = <1>; }; - pwm@10048000 { + pwm: pwm@10048000 { compatible = "mediatek,mt7981-pwm"; reg = <0 0x10048000 0 0x1000>; clocks = <&infracfg CLK_INFRA_PWM_STA>, -- 2.51.0