| Subject | mlx5-next updates 2025-09-22 |
|---|---|
| Author | tariqt@nvidia.com |
| Date | 2025-09-22 06:06:30 +0000 UTC |
| Version | 1 |
| Cc | andrew@lunn.ch davem@davemloft.net edumazet@google.com gal@nvidia.com kuba@kernel.org leon@kernel.org linux-kernel@vger.kernel.org linux-rdma@vger.kernel.org mbloch@nvidia.com netdev@vger.kernel.org pabeni@redhat.com saeedm@nvidia.com tariqt@nvidia.com |
| Name | Content |
|---|---|
| [PATCH mlx5-next 1/2] net/mlx5: Add IFC bit for TIR/SQ order capability | [Body] |
| [PATCH mlx5-next 2/2] net/mlx5: IFC add balance ID and LAG per MP group bits | [Body] |
| ID (for dev) | ab939c8c-72ef-4d5f-a7ce-9baeab720c59 |
|---|---|
| Status | finished |
| Triaged | OK [Log] |
| Execution Log | [Link] |
| Test | Base | Patched | Verdict |
|---|---|---|---|
| Build Base | 315f423be0d1ebe720d8fd4fa6bed68586b13d34 [Config] | passed [Log] | |
| Build Patched | 315f423be0d1ebe720d8fd4fa6bed68586b13d34 [Config] [patched] | passed [Log] | |
| Boot test: Patched | 315f423be0d1ebe720d8fd4fa6bed68586b13d34 [Config] [patched] | passed | |
| Boot test: Base | 315f423be0d1ebe720d8fd4fa6bed68586b13d34 [Config] | passed | |
| Fuzzing | 315f423be0d1ebe720d8fd4fa6bed68586b13d34 [Config] | 315f423be0d1ebe720d8fd4fa6bed68586b13d34 [Config] [patched] | skipped [Log] [Artifacts] |