From: Nazim Amirul Add compatible string for the Intel SoCFPGA Agilex5 SoCDK TSN Config2 board variant. This board enables gmac1 as a TSN port with an FPGA GMII-to-RGMII converter providing the RGMII clock delays. Signed-off-by: Nazim Amirul Acked-by: Krzysztof Kozlowski --- v6: No changes from v5. v4: Fix wrong email address in Acked-by tag from Krzysztof Kozlowski. v3: Add missing Acked-by from Krzysztof Kozlowski inadvertently dropped in v2. Documentation/devicetree/bindings/arm/altera.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 3030cf46fe74..e431469a7175 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -114,6 +114,7 @@ properties: - intel,socfpga-agilex5-socdk-debug - intel,socfpga-agilex5-socdk-modular - intel,socfpga-agilex5-socdk-nand + - intel,socfpga-agilex5-socdk-tsn-cfg2 - const: intel,socfpga-agilex5 - description: Agilex72 boards -- 2.43.7 From: Nazim Amirul Add device tree for the Intel SoCFPGA Agilex5 SoCDK TSN Config2 board variant. This configuration enables gmac1 as a TSN port alongside the standard gmac2 Ethernet port. The TSN port (gmac1) connects to its PHY through a GMII-to-RGMII converter implemented as FPGA soft IP. This converter provides the RGMII TX/RX clock delays, so phy-mode is set to "rgmii-id" to reflect MAC-side delays. Use altr,socfpga-stmmac-agilex5-tsn because this integration is not the same as a plain Agilex5 GMAC port without the converter. Signed-off-by: Nazim Amirul --- v6: No changes from v5. arch/arm64/boot/dts/intel/Makefile | 1 + .../intel/socfpga_agilex5_socdk_tsn_cfg2.dts | 130 ++++++++++++++++++ 2 files changed, 131 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index 270c70fdf084..ce7cf3a63275 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex5_socdk_013b.dtb \ socfpga_agilex5_socdk_modular.dtb \ socfpga_agilex5_socdk_nand.dtb \ + socfpga_agilex5_socdk_tsn_cfg2.dtb \ socfpga_agilex72_socdk.dtb \ socfpga_agilex7m_socdk.dtb \ socfpga_n5x_socdk.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts new file mode 100644 index 000000000000..9d39f843b424 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026, Altera Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex5 SoCDK TSN Config2"; + compatible = "intel,socfpga-agilex5-socdk-tsn-cfg2", "intel,socfpga-agilex5"; + + aliases { + serial0 = &uart0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "hps_led0"; + gpios = <&porta 11 GPIO_ACTIVE_HIGH>; + }; + + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0x0 0x80000000 0x0 0x0>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + compatible = "altr,socfpga-stmmac-agilex5-tsn", + "snps,dwxgmac-2.10"; + phy-mode = "rgmii-id"; + phy-handle = <&emac1_phy0>; + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + emac1_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&emac2_phy0>; + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + m25p,fast-read; + cdns,read-delay = <2>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "u-boot"; + reg = <0x0 0x04200000>; + }; + + root: partition@4200000 { + label = "root"; + reg = <0x04200000 0x0be00000>; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog0 { + status = "okay"; +}; -- 2.43.7 From: Nazim Amirul The Agilex5 SoCDK TSN Config2 gmac1 path includes an FPGA soft-IP GMII-to-RGMII converter between the DWXGMAC and the PHY. The converter provides the RGMII TX/RX delays and presents GMII toward the MAC, unlike a plain altr,socfpga-stmmac-agilex5 port with no such converter. Add altr,socfpga-stmmac-agilex5-tsn for that integration in the same compatible items entry as altr,socfpga-stmmac-agilex5 (shared snps,dwxgmac-2.10). Do not use altr,socfpga-stmmac-agilex5 as a DT fallback for the TSN port; the converter presents GMII to the MAC and supplies the RGMII delays, unlike a plain Agilex5 GMAC port. Signed-off-by: Nazim Amirul --- v6: Put altr,socfpga-stmmac-agilex5-tsn in the same enum as altr,socfpga-stmmac-agilex5, per Krzysztof Kozlowski. v5: Drop altr,socfpga-stmmac-agilex5 fallback and rewrite commit message to explain hardware incompatibility, per Krzysztof Kozlowski. v4: No changes from v2. .../devicetree/bindings/net/altr,socfpga-stmmac.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml index 63084f762373..2c27bfd5af89 100644 --- a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +++ b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml @@ -24,6 +24,7 @@ select: - altr,socfpga-stmmac - altr,socfpga-stmmac-a10-s10 - altr,socfpga-stmmac-agilex5 + - altr,socfpga-stmmac-agilex5-tsn required: - compatible @@ -44,7 +45,9 @@ properties: - const: snps,dwmac-3.74a - const: snps,dwmac - items: - - const: altr,socfpga-stmmac-agilex5 + - enum: + - altr,socfpga-stmmac-agilex5 + - altr,socfpga-stmmac-agilex5-tsn - const: snps,dwxgmac-2.10 clocks: -- 2.43.7 From: Nazim Amirul The Agilex5 SoCDK TSN Config2 board uses a GMII-to-RGMII converter implemented as FPGA soft IP between gmac1 and its PHY. This converter provides the RGMII TX/RX clock delays, so the MAC interface selector must be configured for GMII while the PHY is configured without delays. Add the "altr,socfpga-stmmac-agilex5-tsn" compatible with dedicated match .data ops that extend the standard Agilex5 setup: force GMII for the MAC interface selector and strip delay bits from phy_interface so the PHY is not configured to add delays already provided by the FPGA converter. Signed-off-by: Nazim Amirul Reviewed-by: Andrew Lunn --- v6: No changes from v5. v5: Replace of_device_is_compatible() probe check with dedicated socfpga_agilex5_tsn_gmac_ops via match .data, per Krzysztof Kozlowski and Dinh Nguyen. v4: Add Reviewed-by from Andrew Lunn. .../ethernet/stmicro/stmmac/dwmac-socfpga.c | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c index 1d7f0a57d288..0632105b420f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -69,12 +69,13 @@ struct socfpga_dwmac { void __iomem *tse_pcs_base; void __iomem *sgmii_adapter_base; bool f2h_ptp_ref_clk; + phy_interface_t mac_interface; const struct socfpga_dwmac_ops *ops; }; static phy_interface_t socfpga_get_plat_phymode(struct socfpga_dwmac *dwmac) { - return dwmac->plat_dat->phy_interface; + return dwmac->mac_interface; } static void socfpga_sgmii_config(struct socfpga_dwmac *dwmac, bool enable) @@ -650,6 +651,8 @@ static int socfpga_dwmac_probe(struct platform_device *pdev) plat_dat->pcs_exit = socfpga_dwmac_pcs_exit; plat_dat->select_pcs = socfpga_dwmac_select_pcs; + dwmac->mac_interface = plat_dat->phy_interface; + ops->setup_plat_dat(dwmac); return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); @@ -670,10 +673,28 @@ static const struct socfpga_dwmac_ops socfpga_agilex5_ops = { .setup_plat_dat = socfpga_agilex5_setup_plat_dat, }; +static void socfpga_agilex5_tsn_gmac_setup_plat_dat(struct socfpga_dwmac *dwmac) +{ + struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat; + + socfpga_agilex5_setup_plat_dat(dwmac); + + /* FPGA converter supplies RGMII delays; MAC uses GMII, PHY gets plain RGMII */ + dwmac->mac_interface = PHY_INTERFACE_MODE_GMII; + if (phy_interface_mode_is_rgmii(plat_dat->phy_interface)) + plat_dat->phy_interface = PHY_INTERFACE_MODE_RGMII; +} + +static const struct socfpga_dwmac_ops socfpga_agilex5_tsn_gmac_ops = { + .set_phy_mode = socfpga_gen10_set_phy_mode, + .setup_plat_dat = socfpga_agilex5_tsn_gmac_setup_plat_dat, +}; + static const struct of_device_id socfpga_dwmac_match[] = { { .compatible = "altr,socfpga-stmmac", .data = &socfpga_gen5_ops }, { .compatible = "altr,socfpga-stmmac-a10-s10", .data = &socfpga_gen10_ops }, { .compatible = "altr,socfpga-stmmac-agilex5", .data = &socfpga_agilex5_ops }, + { .compatible = "altr,socfpga-stmmac-agilex5-tsn", .data = &socfpga_agilex5_tsn_gmac_ops }, { } }; MODULE_DEVICE_TABLE(of, socfpga_dwmac_match); -- 2.43.7