Syzbot CI

Subject	Organize the SMMUv3 invalidation flow so iommupt can use it
Author	jgg@nvidia.com
Date	2026-09-17 00:27:42 +0000 UTC
Version
Cc	catalin.marinas@arm.com corbet@lwn.net dmatlack@google.com iommu@lists.linux.dev jean-philippe@linaro.org jgg@nvidia.com jonathan.cameron@huawei.com joro@8bytes.org jpb@kernel.org linux-arm-kernel@lists.infradead.org linux-doc@vger.kernel.org mark.rutland@arm.com nicolinc@nvidia.com pasha.tatashin@soleen.com patches@lists.linux.dev praan@google.com rdunlap@infradead.org robin.murphy@arm.com skhan@linuxfoundation.org skhawaja@google.com smostafa@google.com stable@vger.kernel.org vijayanand.jitta@oss.qualcomm.com will@kernel.org

Patches (9)

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Name	Content [All]
[PATCH v6 1/9] iommu/arm-smmu-v3: Handle ARM erratum for CONT under invalidation with SVA	[Body]
[PATCH v6 2/9] iommu/arm-smmu-v3: Pass the parameters for the invalidation in a struct	[Body]
[PATCH v6 3/9] iommu/arm-smmu-v3: Move pgsize out of arm_smmu_inv	[Body]
[PATCH v6 4/9] iommu/arm-smmu-v3: Optimize range invalidation for latency	[Body]
[PATCH v6 5/9] iommu/arm-smmu-v3: Keep track in the arm_smmu_invs if RIL is used	[Body]
[PATCH v6 6/9] iommu/arm-smmu-v3: Precompute the invalidation commands	[Body]
[PATCH v6 7/9] iommu/arm-smmu-v3: Populate the tlbi at the top of the call chain	[Body]
[PATCH v6 8/9] iommu/arm-smmu-v3: Change how the tlbi describes the invalidation	[Body]
[PATCH v6 9/9] iommu/arm-smmu-v3: Support the DS expansion of RIL's SCALE	[Body]

Series Summary

skipped

Session skipped: AI determined the patch has no functional impact

Sessions

Session 2026-09-17

skipped

ID (for dev)	89cb3eff-a12d-43ac-b303-5ddb4eeaff2b
Status	skipped
Triaged	Skipped: AI determined the patch has no functional impact [Log] [Trajectory]
Execution Log	[Link]

Test	Base	Patched	Verdict