Reference the common PHY properties so RX and TX SerDes lane polarity of the SGMII/1000Base-X/2500Base-X PCS can be configured. Signed-off-by: Daniel Golle --- Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml b/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml index f601e5f9fa6a..bf199b096dc5 100644 --- a/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +++ b/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml @@ -105,6 +105,7 @@ patternProperties: patternProperties: "^(ethernet-)?port@[0-6]$": $ref: dsa-port.yaml# + $ref: /schemas/phy/phy-common-props.yaml# unevaluatedProperties: false properties: -- 2.52.0 Configure SerDes PCS RX and TX polarities using the newly introduced generic properties. Signed-off-by: Daniel Golle --- drivers/net/dsa/lantiq/Kconfig | 1 + drivers/net/dsa/lantiq/mxl-gsw1xx.c | 38 +++++++++++++++++++++-------- 2 files changed, 29 insertions(+), 10 deletions(-) diff --git a/drivers/net/dsa/lantiq/Kconfig b/drivers/net/dsa/lantiq/Kconfig index bad13817af25..98efeef2661b 100644 --- a/drivers/net/dsa/lantiq/Kconfig +++ b/drivers/net/dsa/lantiq/Kconfig @@ -15,6 +15,7 @@ config NET_DSA_MXL_GSW1XX tristate "MaxLinear GSW1xx Ethernet switch support" select NET_DSA_TAG_MXL_GSW1XX select NET_DSA_LANTIQ_COMMON + select PHY_COMMON_PROPS help This enables support for the Intel/MaxLinear GSW1xx family of 1GE switches. diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.c b/drivers/net/dsa/lantiq/mxl-gsw1xx.c index 79cf72cc77be..6284b9afdbbb 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.c +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include #include #include @@ -229,11 +231,17 @@ static int gsw1xx_pcs_phy_xaui_write(struct gsw1xx_priv *priv, u16 addr, 1000, 100000); } -static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv) +static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv, phy_interface_t interface) { + struct dsa_port *pcs_port; + unsigned int pol; int ret; u16 val; + pcs_port = dsa_to_port(priv->gswip.ds, GSW1XX_SGMII_PORT); + if (!pcs_port) + return -EINVAL; + /* Assert and deassert SGMII shell reset */ ret = regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ, GSW1XX_RST_REQ_SGMII_SHELL); @@ -260,15 +268,19 @@ static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv) FIELD_PREP(GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT, GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT_DEF); + ret = phy_get_rx_polarity(of_fwnode_handle(pcs_port->dn), + phy_modes(interface), + BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT), + PHY_POL_NORMAL, &pol); + if (ret) + return ret; + /* RX lane seems to be inverted internally, so bit * GSW1XX_SGMII_PHY_RX0_CFG2_INVERT needs to be set for normal * (ie. non-inverted) operation. - * - * TODO: Take care of inverted RX pair once generic property is - * available */ - - val |= GSW1XX_SGMII_PHY_RX0_CFG2_INVERT; + if (pol == PHY_POL_NORMAL) + val |= GSW1XX_SGMII_PHY_RX0_CFG2_INVERT; ret = regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_RX0_CFG2, val); if (ret < 0) @@ -277,9 +289,15 @@ static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv) val = FIELD_PREP(GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL, GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL_DEF); - /* TODO: Take care of inverted TX pair once generic property is - * available - */ + ret = phy_get_tx_polarity(of_fwnode_handle(pcs_port->dn), + phy_modes(interface), + BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT), + PHY_POL_NORMAL, &pol); + if (ret) + return ret; + + if (pol == PHY_POL_INVERT) + val |= GSW1XX_SGMII_PHY_TX0_CFG3_INVERT; ret = regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_TX0_CFG3, val); if (ret < 0) @@ -336,7 +354,7 @@ static int gsw1xx_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, priv->tbi_interface = PHY_INTERFACE_MODE_NA; if (!reconf) - ret = gsw1xx_pcs_reset(priv); + ret = gsw1xx_pcs_reset(priv, interface); if (ret) return ret; -- 2.52.0 No check for actually present hardware is being performed in the probe function of the mxl-gsw1xx switch driver. So even if the switch isn't present at the configured MDIO bus address the driver wrongly tells the user that a "GSWIP version 0 mod 0" was found, outputting errors about PHY capabilities not matching. Read and validate the chip MANU_ID and PNUM_ID registers and output information while probing, but return an error and abort probing in case the hardware is not actually present. Signed-off-by: Daniel Golle --- drivers/net/dsa/lantiq/mxl-gsw1xx.c | 27 ++++++++++++++++++++++++++- drivers/net/dsa/lantiq/mxl-gsw1xx.h | 9 +++++++++ 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.c b/drivers/net/dsa/lantiq/mxl-gsw1xx.c index 6284b9afdbbb..68034ce25e5a 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.c +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.c @@ -689,7 +689,9 @@ static int gsw1xx_probe(struct mdio_device *mdiodev) { struct device *dev = &mdiodev->dev; struct gsw1xx_priv *priv; - u32 version; + u32 version, val; + u8 shellver; + u16 pnum; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -737,6 +739,27 @@ static int gsw1xx_probe(struct mdio_device *mdiodev) if (IS_ERR(priv->shell)) return PTR_ERR(priv->shell); + ret = regmap_read(priv->shell, GSW1XX_SHELL_MANU_ID, &val); + if (ret < 0) + return ret; + + /* validate chip ID */ + if (FIELD_GET(GSW1XX_SHELL_MANU_ID_FIX1, val) != 1) + return -ENODEV; + + if (FIELD_GET(GSW1XX_SHELL_MANU_ID_MANID, val) != + GSW1XX_SHELL_MANU_ID_MANID_VAL) + return -ENODEV; + + pnum = FIELD_GET(GSW1XX_SHELL_MANU_ID_PNUML, val); + + ret = regmap_read(priv->shell, GSW1XX_SHELL_PNUM_ID, &val); + if (ret < 0) + return ret; + + pnum |= FIELD_GET(GSW1XX_SHELL_PNUM_ID_PNUMM, val) << 4; + shellver = FIELD_GET(GSW1XX_SHELL_PNUM_ID_VER, val); + ret = gsw1xx_serdes_pcs_init(priv); if (ret < 0) return ret; @@ -757,6 +780,8 @@ static int gsw1xx_probe(struct mdio_device *mdiodev) if (ret) return ret; + dev_info(dev, "standalone switch part number 0x%x v1.%u\n", pnum, shellver); + dev_set_drvdata(dev, &priv->gswip); return 0; diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.h b/drivers/net/dsa/lantiq/mxl-gsw1xx.h index d1fded56e967..caa8f1008587 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.h +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.h @@ -110,6 +110,15 @@ #define GSW1XX_SHELL_BASE 0xfa00 #define GSW1XX_SHELL_RST_REQ 0x01 #define GSW1XX_RST_REQ_SGMII_SHELL BIT(5) +#define GSW1XX_SHELL_MANU_ID 0x10 +#define GSW1XX_SHELL_MANU_ID_PNUML GENMASK(15, 12) +#define GSW1XX_SHELL_MANU_ID_MANID GENMASK(11, 1) +#define GSW1XX_SHELL_MANU_ID_MANID_VAL 0x389 +#define GSW1XX_SHELL_MANU_ID_FIX1 BIT(0) +#define GSW1XX_SHELL_PNUM_ID 0x11 +#define GSW1XX_SHELL_PNUM_ID_VER GENMASK(15, 12) +#define GSW1XX_SHELL_PNUM_ID_PNUMM GENMASK(11, 0) + /* RGMII PAD Slew Control Register */ #define GSW1XX_SHELL_RGMII_SLEW_CFG 0x78 #define RGMII_SLEW_CFG_DRV_TXC BIT(2) -- 2.52.0