Subject Rework dpll pin control
Author sergey.temerkhanov@intel.com
Date 2026-08-21 15:24:49 +0000 UTC
Version
Cc intel-wired-lan@lists.osuosl.org netdev@vger.kernel.org sergey.temerkhanov@intel.com
Patches (6)
Name Content [All]
[PATCH iwl-next v3 1/6] ice: dpll: Add the MUX tables to the documentation [Body]
[PATCH iwl-next v3 2/6] ice: dpll: Rework multiplexed pin notifications [Body]
[PATCH iwl-next v3 3/6] ice: dpll: Use switch statements to handle pin states [Body]
[PATCH iwl-next v3 4/6] ice: dpll: Check for bounds when updating the pin states [Body]
[PATCH iwl-next v3 5/6] ice: dpll: Rework U.FL muxed pin (SMA) control [Body]
[PATCH iwl-next v3 6/6] ice: dpll: Rework the SMA control logic to match the requirements [Body]
Series Summary
skipped
Session skipped: AI determined the patch has no functional impact
Sessions
Session 2026-08-21
skipped
ID (for dev) d99b608e-296d-4d7c-b4f9-128f4d5c2b0e
Status skipped
Triaged Skipped: AI determined the patch has no functional impact [Log] [Trajectory]
Execution Log [Link]
Test Base Patched Verdict