From: Lad Prabhakar Increase the `maxItems` value for the `interrupts` and `interrupt-names` properties to 19 to support additional per-channel Tx/Rx completion interrupts on the Renesas RZ/T2H SoC, which features the `snps,dwmac-5.20` IP with 8 Rx queues and 8 Tx queues. Signed-off-by: Lad Prabhakar --- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 4e3cbaa06229..578553840c9e 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -118,11 +118,11 @@ properties: interrupts: minItems: 1 - maxItems: 11 + maxItems: 19 interrupt-names: minItems: 1 - maxItems: 11 + maxItems: 19 items: oneOf: - description: Combined signal for various interrupt events @@ -134,9 +134,9 @@ properties: - description: The interrupt that occurs when HW safety error triggered const: sfty - description: Per channel receive completion interrupt - pattern: '^rx-queue-[0-3]$' + pattern: '^rx-queue-[0-7]$' - description: Per channel transmit completion interrupt - pattern: '^tx-queue-[0-3]$' + pattern: '^tx-queue-[0-7]$' clocks: minItems: 1 -- 2.51.0 From: Lad Prabhakar Document the Ethernet MAC (GMAC) IP present on the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. The GMAC IP on RZ/N2H is identical to that found on the RZ/T2H SoC. While the RZ/V2H(P), RZ/T2H, and RZ/N2H SoCs all integrate the Synopsys DesignWare MAC (version 5.20), the hardware is synthesized with different options compared to the RZ/V2H(P): - RZ/T2H requires only 3 clocks instead of 7 - RZ/T2H supports 8 RX/TX queue pairs instead of 4 - RZ/T2H needs 2 reset controls with reset-names property, vs. a single unnamed reset - RZ/T2H has the split header feature enabled, while it is disabled on RZ/V2H(P) To accommodate these differences, introduce a new generic compatible string `renesas,rzt2h-gbeth`, used as a fallback for both RZ/T2H and RZ/N2H SoCs. The DT schema is updated to validate the clocks, resets, reset-names, interrupts, and interrupt-names properties accordingly. Also extend `snps,dwmac.yaml` with the new `renesas,rzt2h-gbeth` compatible. Signed-off-by: Lad Prabhakar --- .../bindings/net/renesas,rzv2h-gbeth.yaml | 177 ++++++++++++++---- .../devicetree/bindings/net/snps,dwmac.yaml | 1 + 2 files changed, 138 insertions(+), 40 deletions(-) diff --git a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml index 23e39bcea96b..e01763389164 100644 --- a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml +++ b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml @@ -17,63 +17,112 @@ select: - renesas,r9a09g047-gbeth - renesas,r9a09g056-gbeth - renesas,r9a09g057-gbeth + - renesas,r9a09g077-gbeth + - renesas,r9a09g087-gbeth - renesas,rzv2h-gbeth required: - compatible properties: compatible: - items: - - enum: - - renesas,r9a09g047-gbeth # RZ/G3E - - renesas,r9a09g056-gbeth # RZ/V2N - - renesas,r9a09g057-gbeth # RZ/V2H(P) - - const: renesas,rzv2h-gbeth - - const: snps,dwmac-5.20 + oneOf: + - items: + - enum: + - renesas,r9a09g047-gbeth # RZ/G3E + - renesas,r9a09g056-gbeth # RZ/V2N + - renesas,r9a09g057-gbeth # RZ/V2H(P) + - const: renesas,rzv2h-gbeth + - const: snps,dwmac-5.20 + + - items: + - enum: + - renesas,r9a09g077-gbeth # RZ/T2H + - renesas,r9a09g087-gbeth # RZ/N2H + - const: renesas,rzt2h-gbeth + - const: snps,dwmac-5.20 reg: maxItems: 1 clocks: - items: - - description: CSR clock - - description: AXI system clock - - description: PTP clock - - description: TX clock - - description: RX clock - - description: TX clock phase-shifted by 180 degrees - - description: RX clock phase-shifted by 180 degrees + oneOf: + - items: + - description: CSR clock + - description: AXI system clock + - description: PTP clock + - description: TX clock + - description: RX clock + - description: TX clock phase-shifted by 180 degrees + - description: RX clock phase-shifted by 180 degrees + + - items: + - description: CSR clock + - description: AXI system clock + - description: TX clock clock-names: - items: - - const: stmmaceth - - const: pclk - - const: ptp_ref - - const: tx - - const: rx - - const: tx-180 - - const: rx-180 - - interrupts: - minItems: 11 + oneOf: + - items: + - const: stmmaceth + - const: pclk + - const: ptp_ref + - const: tx + - const: rx + - const: tx-180 + - const: rx-180 + + - items: + - const: stmmaceth + - const: pclk + - const: tx + interrupt-names: - items: - - const: macirq - - const: eth_wake_irq - - const: eth_lpi - - const: rx-queue-0 - - const: rx-queue-1 - - const: rx-queue-2 - - const: rx-queue-3 - - const: tx-queue-0 - - const: tx-queue-1 - - const: tx-queue-2 - - const: tx-queue-3 + oneOf: + - items: + - const: macirq + - const: eth_wake_irq + - const: eth_lpi + - const: rx-queue-0 + - const: rx-queue-1 + - const: rx-queue-2 + - const: rx-queue-3 + - const: tx-queue-0 + - const: tx-queue-1 + - const: tx-queue-2 + - const: tx-queue-3 + + - items: + - const: macirq + - const: eth_wake_irq + - const: eth_lpi + - const: rx-queue-0 + - const: rx-queue-1 + - const: rx-queue-2 + - const: rx-queue-3 + - const: rx-queue-4 + - const: rx-queue-5 + - const: rx-queue-6 + - const: rx-queue-7 + - const: tx-queue-0 + - const: tx-queue-1 + - const: tx-queue-2 + - const: tx-queue-3 + - const: tx-queue-4 + - const: tx-queue-5 + - const: tx-queue-6 + - const: tx-queue-7 resets: - items: - - description: AXI power-on system reset + oneOf: + - items: + - description: AXI power-on system reset + + - items: + - description: GMAC stmmaceth reset + - description: AHB reset + + reset-names: true required: - compatible @@ -87,6 +136,54 @@ required: allOf: - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + const: renesas,rzt2h-gbeth + then: + properties: + clocks: + maxItems: 3 + + clock-names: + maxItems: 3 + + interrupts: + minItems: 19 + + interrupt-names: + minItems: 19 + + resets: + minItems: 2 + + reset-names: + minItems: 2 + + required: + - reset-names + else: + properties: + clocks: + minItems: 7 + + clock-names: + minItems: 7 + + interrupts: + minItems: 11 + maxItems: 11 + + interrupt-names: + minItems: 11 + maxItems: 11 + + resets: + maxItems: 1 + + reset-names: false + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 578553840c9e..14be80fe9c82 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -77,6 +77,7 @@ properties: - renesas,r9a06g032-gmac - renesas,rzn1-gmac - renesas,rzv2h-gbeth + - renesas,rzt2h-gbeth - rockchip,px30-gmac - rockchip,rk3128-gmac - rockchip,rk3228-gmac -- 2.51.0 From: Lad Prabhakar Prepare for adding RZ/T2H SoC support by making the driver configuration selectable via OF match data. While the RZ/V2H(P) and RZ/T2H use the same version of the Synopsys DesignWare MAC (version 5.20), the hardware is synthesized with different options. To accommodate these differences, introduce a struct holding per-SoC configuration such as clock list, number of clocks, TX clock rate control, and STMMAC flags, and retrieve it from the device tree match entry during probe. Signed-off-by: Lad Prabhakar --- .../stmicro/stmmac/dwmac-renesas-gbeth.c | 57 +++++++++++++++---- 1 file changed, 47 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c index df4ca897a60c..022e595a9e1b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c @@ -16,12 +16,34 @@ #include #include #include +#include #include #include +#include #include "stmmac_platform.h" +/** + * struct renesas_gbeth_of_data - OF data for Renesas GBETH + * + * @clks: Array of clock names + * @num_clks: Number of clocks + * @stmmac_flags: Flags for the stmmac driver + * @handle_reset: Flag to indicate if reset control is + * handled by the glue driver or core driver. + * @set_clk_tx_rate: Flag to indicate if Tx clock is fixed or + * set_clk_tx_rate is needed. + */ +struct renesas_gbeth_of_data { + const char * const *clks; + u8 num_clks; + u32 stmmac_flags; + bool handle_reset; + bool set_clk_tx_rate; +}; + struct renesas_gbeth { + const struct renesas_gbeth_of_data *of_data; struct plat_stmmacenet_data *plat_dat; struct reset_control *rstc; struct device *dev; @@ -70,6 +92,7 @@ static void renesas_gbeth_exit(struct platform_device *pdev, void *priv) static int renesas_gbeth_probe(struct platform_device *pdev) { + const struct renesas_gbeth_of_data *of_data; struct plat_stmmacenet_data *plat_dat; struct stmmac_resources stmmac_res; struct device *dev = &pdev->dev; @@ -91,14 +114,17 @@ static int renesas_gbeth_probe(struct platform_device *pdev) if (!gbeth) return -ENOMEM; - plat_dat->num_clks = ARRAY_SIZE(renesas_gbeth_clks); + of_data = of_device_get_match_data(&pdev->dev); + gbeth->of_data = of_data; + + plat_dat->num_clks = of_data->num_clks; plat_dat->clks = devm_kcalloc(dev, plat_dat->num_clks, sizeof(*plat_dat->clks), GFP_KERNEL); if (!plat_dat->clks) return -ENOMEM; for (i = 0; i < plat_dat->num_clks; i++) - plat_dat->clks[i].id = renesas_gbeth_clks[i]; + plat_dat->clks[i].id = of_data->clks[i]; err = devm_clk_bulk_get(dev, plat_dat->num_clks, plat_dat->clks); if (err < 0) @@ -109,25 +135,36 @@ static int renesas_gbeth_probe(struct platform_device *pdev) return dev_err_probe(dev, -EINVAL, "error finding tx clock\n"); - gbeth->rstc = devm_reset_control_get_exclusive(dev, NULL); - if (IS_ERR(gbeth->rstc)) - return PTR_ERR(gbeth->rstc); + if (of_data->handle_reset) { + gbeth->rstc = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(gbeth->rstc)) + return PTR_ERR(gbeth->rstc); + } gbeth->dev = dev; gbeth->plat_dat = plat_dat; plat_dat->bsp_priv = gbeth; - plat_dat->set_clk_tx_rate = stmmac_set_clk_tx_rate; + if (of_data->set_clk_tx_rate) + plat_dat->set_clk_tx_rate = stmmac_set_clk_tx_rate; plat_dat->init = renesas_gbeth_init; plat_dat->exit = renesas_gbeth_exit; - plat_dat->flags |= STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY | - STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP | - STMMAC_FLAG_SPH_DISABLE; + plat_dat->flags |= gbeth->of_data->stmmac_flags; return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); } +static const struct renesas_gbeth_of_data renesas_gbeth_of_data = { + .clks = renesas_gbeth_clks, + .num_clks = ARRAY_SIZE(renesas_gbeth_clks), + .handle_reset = true, + .set_clk_tx_rate = true, + .stmmac_flags = STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY | + STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP | + STMMAC_FLAG_SPH_DISABLE, +}; + static const struct of_device_id renesas_gbeth_match[] = { - { .compatible = "renesas,rzv2h-gbeth", }, + { .compatible = "renesas,rzv2h-gbeth", .data = &renesas_gbeth_of_data }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, renesas_gbeth_match); -- 2.51.0 From: Lad Prabhakar Extend the Renesas GBETH stmmac glue driver to support the RZ/T2H SoC, where the GMAC is connected through a MIIC PCS. Introduce a new `has_pcs` flag in `struct renesas_gbeth_of_data` to indicate when PCS handling is required. When enabled, the driver parses the `pcs-handle` phandle, creates a PCS instance with `miic_create()`, and wires it into phylink. Proper cleanup is done with `miic_destroy()`. New init/exit/select hooks are added to `plat_stmmacenet_data` for PCS integration. Update Kconfig to select `PCS_RZN1_MIIC` when building the Renesas GBETH driver so the PCS support is always available. Signed-off-by: Lad Prabhakar --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 + .../stmicro/stmmac/dwmac-renesas-gbeth.c | 52 +++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 67fa879b1e52..a01c83b109f9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -136,6 +136,7 @@ config DWMAC_RENESAS_GBETH tristate "Renesas RZ/V2H(P) GBETH support" default ARCH_RENESAS depends on OF && (ARCH_RENESAS || COMPILE_TEST) + select PCS_RZN1_MIIC help Support for Gigabit Ethernet Interface (GBETH) on Renesas RZ/V2H(P) SoCs. diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c index 022e595a9e1b..ad89f7b8f279 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -33,6 +34,7 @@ * handled by the glue driver or core driver. * @set_clk_tx_rate: Flag to indicate if Tx clock is fixed or * set_clk_tx_rate is needed. + * @has_pcs: Flag to indicate if the MAC has a PCS */ struct renesas_gbeth_of_data { const char * const *clks; @@ -40,6 +42,7 @@ struct renesas_gbeth_of_data { u32 stmmac_flags; bool handle_reset; bool set_clk_tx_rate; + bool has_pcs; }; struct renesas_gbeth { @@ -53,6 +56,41 @@ static const char *const renesas_gbeth_clks[] = { "tx", "tx-180", "rx", "rx-180", }; +static const char *const renesas_gmac_clks[] = { + "tx", +}; + +static int renesas_gmac_pcs_init(struct stmmac_priv *priv) +{ + struct device_node *np = priv->device->of_node; + struct device_node *pcs_node; + struct phylink_pcs *pcs; + + pcs_node = of_parse_phandle(np, "pcs-handle", 0); + if (pcs_node) { + pcs = miic_create(priv->device, pcs_node); + of_node_put(pcs_node); + if (IS_ERR(pcs)) + return PTR_ERR(pcs); + + priv->hw->phylink_pcs = pcs; + } + + return 0; +} + +static void renesas_gmac_pcs_exit(struct stmmac_priv *priv) +{ + if (priv->hw->phylink_pcs) + miic_destroy(priv->hw->phylink_pcs); +} + +static struct phylink_pcs *renesas_gmac_select_pcs(struct stmmac_priv *priv, + phy_interface_t interface) +{ + return priv->hw->phylink_pcs; +} + static int renesas_gbeth_init(struct platform_device *pdev, void *priv) { struct plat_stmmacenet_data *plat_dat; @@ -149,6 +187,11 @@ static int renesas_gbeth_probe(struct platform_device *pdev) plat_dat->init = renesas_gbeth_init; plat_dat->exit = renesas_gbeth_exit; plat_dat->flags |= gbeth->of_data->stmmac_flags; + if (of_data->has_pcs) { + plat_dat->pcs_init = renesas_gmac_pcs_init; + plat_dat->pcs_exit = renesas_gmac_pcs_exit; + plat_dat->select_pcs = renesas_gmac_select_pcs; + } return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); } @@ -163,8 +206,17 @@ static const struct renesas_gbeth_of_data renesas_gbeth_of_data = { STMMAC_FLAG_SPH_DISABLE, }; +static const struct renesas_gbeth_of_data renesas_gmac_of_data = { + .clks = renesas_gmac_clks, + .num_clks = ARRAY_SIZE(renesas_gmac_clks), + .stmmac_flags = STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY | + STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP, + .has_pcs = true, +}; + static const struct of_device_id renesas_gbeth_match[] = { { .compatible = "renesas,rzv2h-gbeth", .data = &renesas_gbeth_of_data }, + { .compatible = "renesas,rzt2h-gbeth", .data = &renesas_gmac_of_data }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, renesas_gbeth_match); -- 2.51.0