Add property enet-phy-lane-order to the device tree bindings to define the lane order of the PHY. To simplify PCB design some manufacturers allow to wire the pairs in a reverse order, and change the order in software. The property can be set to 0 to force the normal lane order (ABCD), or 1 to force the reverse lane order (DCBA). Signed-off-by: Damien Dejean --- Documentation/devicetree/bindings/net/ethernet-phy.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 58634fee9fc4..8347d4e134d2 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -126,6 +126,12 @@ properties: e.g. wrong bootstrap configuration caused by issues in PCB layout design. + enet-phy-lane-order: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + For normal (0) or reverse (1) order of the pairs (ABCD -> DCBA). + eee-broken-100tx: $ref: /schemas/types.yaml#/definitions/flag description: -- 2.47.3 The RTL8224 has a register to configure a pair swap (from ABCD order to DCBA) providing PCB designers more flexbility when wiring the chip. The swap parameter has to be set correctly for each of the 4 ports before the chip can detect a link. After a reset, this register is (unfortunately) left in a random state, thus it has to be initialized. On most of the devices the bootloader does it once for all and we can rely on the value set, on some other it is not and the kernel has to do it. The MDI pair swap can be set in the device tree using the property enet-phy-lane-order. The property is set to 0 to keep the default order (ABCD), or 1 to reverse the pairs (DCBA). Signed-off-by: Damien Dejean --- drivers/net/phy/realtek/Kconfig | 1 + drivers/net/phy/realtek/realtek_main.c | 49 ++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/drivers/net/phy/realtek/Kconfig b/drivers/net/phy/realtek/Kconfig index b05c2a1e9024..a741b34d193e 100644 --- a/drivers/net/phy/realtek/Kconfig +++ b/drivers/net/phy/realtek/Kconfig @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config REALTEK_PHY tristate "Realtek PHYs" + select PHY_PACKAGE help Currently supports RTL821x/RTL822x and fast ethernet PHYs diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c index 75565fbdbf6d..79c2762b610e 100644 --- a/drivers/net/phy/realtek/realtek_main.c +++ b/drivers/net/phy/realtek/realtek_main.c @@ -171,6 +171,8 @@ #define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4) +#define RTL8224_VND1_MDI_PAIR_SWAP 0xa90 + #define RTL8366RB_POWER_SAVE 0x15 #define RTL8366RB_POWER_SAVE_ON BIT(12) @@ -1820,6 +1822,51 @@ static int rtl8224_cable_test_get_status(struct phy_device *phydev, bool *finish return rtl8224_cable_test_report(phydev, finished); } +static int rtl8224_mdi_config_order(struct phy_device *phydev) +{ + struct device_node *np = phydev->mdio.dev.of_node; + u8 port_offset = phydev->mdio.addr & 3; + u32 order = 0; + int ret, val; + + ret = of_property_read_u32(np, "enet-phy-lane-order", &order); + + /* Do nothing in case the property is not present */ + if (ret == -EINVAL) + return 0; + + if (ret) + return ret; + + if (order & ~1) + return -EINVAL; + + val = __phy_package_read_mmd(phydev, 0, MDIO_MMD_VEND1, + RTL8224_VND1_MDI_PAIR_SWAP); + if (val < 0) + return val; + + if (order) + val |= (1 << port_offset); + else + val &= ~(1 << port_offset); + + return __phy_package_write_mmd(phydev, 0, MDIO_MMD_VEND1, + RTL8224_VND1_MDI_PAIR_SWAP, val); +} + +static int rtl8224_config_init(struct phy_device *phydev) +{ + return rtl8224_mdi_config_order(phydev); +} + +static int rtl8224_probe(struct phy_device *phydev) +{ + /* Chip exposes 4 ports, join all of them in the same package */ + return devm_phy_package_join(&phydev->mdio.dev, phydev, + phydev->mdio.addr & ~3, 0); +} + static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) { int val; @@ -2392,6 +2439,8 @@ static struct phy_driver realtek_drvs[] = { PHY_ID_MATCH_EXACT(0x001ccad0), .name = "RTL8224 2.5Gbps PHY", .flags = PHY_POLL_CABLE_TEST, + .probe = rtl8224_probe, + .config_init = rtl8224_config_init, .get_features = rtl822x_c45_get_features, .config_aneg = rtl822x_c45_config_aneg, .read_status = rtl822x_c45_read_status, -- 2.47.3 Add the property enet-phy-lane-polarity to describe the polarity of the PHY lanes. To ease PCB designs some manufacturers allow to wire the pairs with a reverse polarity and provide a way to configure it. The property 'enet-phy-lane-polarity' sets the polarity of each pair. Bit 0 to 3 configure the polarity or pairs A to D, if set to 1 the polarity is reversed for this pair. Signed-off-by: Damien Dejean --- Documentation/devicetree/bindings/net/ethernet-phy.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 8347d4e134d2..67747493352b 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -132,6 +132,14 @@ properties: description: For normal (0) or reverse (1) order of the pairs (ABCD -> DCBA). + enet-phy-lane-polarity: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 0xf + description: + A bitmap to describe pair polarity swap. Bit 0 to swap polarity of pair A, + bit 1 to swap polarity of pair B, bit 2 to swap polarity of pair C and bit + 3 to swap polarity of pair D. + eee-broken-100tx: $ref: /schemas/types.yaml#/definitions/flag description: -- 2.47.3 The RTL8224 has a register to configure the polarity of every pair of each port. It provides device designers more flexbility when wiring the chip. Unfortunately, the register is left in an unknown state after a reset. Thus on devices where the bootloader don't initialize it, the driver has to do it to detect and use a link. The MDI polarity swap can be set in the device tree using the property enet-phy-lane-polarity. The u32 value is a bitfield where bit[0..3] control the polarity of pairs A..D. Signed-off-by: Damien Dejean --- drivers/net/phy/realtek/realtek_main.c | 39 +++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c index 79c2762b610e..8013ba453f05 100644 --- a/drivers/net/phy/realtek/realtek_main.c +++ b/drivers/net/phy/realtek/realtek_main.c @@ -172,6 +172,7 @@ #define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4) #define RTL8224_VND1_MDI_PAIR_SWAP 0xa90 +#define RTL8224_VND1_MDI_POLARITY_SWAP 0xa94 #define RTL8366RB_POWER_SAVE 0x15 #define RTL8366RB_POWER_SAVE_ON BIT(12) @@ -1855,9 +1856,45 @@ static int rtl8224_mdi_config_order(struct phy_device *phydev) RTL8224_VND1_MDI_PAIR_SWAP, val); } +static int rtl8224_mdi_config_polarity(struct phy_device *phydev) +{ + struct device_node *np = phydev->mdio.dev.of_node; + u8 port_offset = phydev->mdio.addr & 3; + u32 polarity = 0; + int ret, val; + + ret = of_property_read_u32(np, "enet-phy-lane-polarity", &polarity); + + /* Do nothing if the property is not present */ + if (ret == -EINVAL) + return 0; + + if (ret) + return ret; + + if (polarity & ~0xf) + return -EINVAL; + + val = __phy_package_read_mmd(phydev, 0, MDIO_MMD_VEND1, + RTL8224_VND1_MDI_POLARITY_SWAP); + if (val < 0) + return val; + + val &= ~(0xf << port_offset); + val |= polarity << port_offset; + return __phy_package_write_mmd(phydev, 0, MDIO_MMD_VEND1, + RTL8224_VND1_MDI_POLARITY_SWAP, val); +} + static int rtl8224_config_init(struct phy_device *phydev) { - return rtl8224_mdi_config_order(phydev); + int ret; + + ret = rtl8224_mdi_config_order(phydev); + if (ret) + return ret; + + return rtl8224_mdi_config_polarity(phydev); } static int rtl8224_probe(struct phy_device *phydev) -- 2.47.3