Convert the existing text-based DT bindings for MediaTek MT8173 Media Data Path to a YAML schema. Signed-off-by: Ariel D'Alessandro --- .../bindings/media/mediatek,mt8173-mdp.yaml | 174 ++++++++++++++++++ .../bindings/media/mediatek-mdp.txt | 95 ---------- 2 files changed, 174 insertions(+), 95 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml delete mode 100644 Documentation/devicetree/bindings/media/mediatek-mdp.txt diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml new file mode 100644 index 0000000000000..f3a08afc305b1 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml @@ -0,0 +1,174 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mt8173-mdp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8173 Media Data Path + +maintainers: + - Ariel D'Alessandro + +description: + Media Data Path is used for scaling and color space conversion. + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt8173-mdp-rdma + - mediatek,mt8173-mdp-rsz + - mediatek,mt8173-mdp-wdma + - mediatek,mt8173-mdp-wrot + - items: + - enum: + - mediatek,mt8173-mdp-rdma + - mediatek,mt8173-mdp-rsz + - mediatek,mt8173-mdp-wdma + - mediatek,mt8173-mdp-wrot + - const: mediatek,mt8173-mdp + + reg: + maxItems: 1 + + clocks: true + + power-domains: + maxItems: 1 + + iommus: + description: | + This property should point to the respective IOMMU block with master port as argument, + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + maxItems: 1 + + mediatek,vpu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Describes point to vpu. + +required: + - compatible + - reg + - clocks + - power-domains + +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8173-mdp-rdma + then: + properties: + clocks: + items: + - description: Main clock + - description: Mutex clock + else: + properties: + clocks: + items: + - description: Main clock + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8173-mdp-rdma + - mediatek,mt8173-mdp-wdma + - mediatek,mt8173-mdp-wrot + then: + required: + - iommus + + - if: + properties: + compatible: + contains: + const: mediatek,mt8173-mdp + then: + required: + - mediatek,vpu + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + mdp_rdma0: rdma@14001000 { + compatible = "mediatek,mt8173-mdp-rdma", + "mediatek,mt8173-mdp"; + reg = <0 0x14001000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MUTEX_32K>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_RDMA0>; + mediatek,vpu = <&vpu>; + }; + + mdp_rdma1: rdma@14002000 { + compatible = "mediatek,mt8173-mdp-rdma"; + reg = <0 0x14002000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RDMA1>, + <&mmsys CLK_MM_MUTEX_32K>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_RDMA1>; + }; + + mdp_rsz0: rsz@14003000 { + compatible = "mediatek,mt8173-mdp-rsz"; + reg = <0 0x14003000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ0>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + }; + + mdp_rsz1: rsz@14004000 { + compatible = "mediatek,mt8173-mdp-rsz"; + reg = <0 0x14004000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ1>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + }; + + mdp_rsz2: rsz@14005000 { + compatible = "mediatek,mt8173-mdp-rsz"; + reg = <0 0x14005000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ2>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + }; + + mdp_wdma0: wdma@14006000 { + compatible = "mediatek,mt8173-mdp-wdma"; + reg = <0 0x14006000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_WDMA>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_WDMA>; + }; + + mdp_wrot0: wrot@14007000 { + compatible = "mediatek,mt8173-mdp-wrot"; + reg = <0 0x14007000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_WROT0>; + }; + + mdp_wrot1: wrot@14008000 { + compatible = "mediatek,mt8173-mdp-wrot"; + reg = <0 0x14008000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_WROT1>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_WROT1>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/media/mediatek-mdp.txt b/Documentation/devicetree/bindings/media/mediatek-mdp.txt deleted file mode 100644 index 53ef26e2c8570..0000000000000 --- a/Documentation/devicetree/bindings/media/mediatek-mdp.txt +++ /dev/null @@ -1,95 +0,0 @@ -* Mediatek Media Data Path - -Media Data Path is used for scaling and color space conversion. - -Required properties (controller node): -- compatible: "mediatek,mt8173-mdp" -- mediatek,vpu: the node of video processor unit, see - Documentation/devicetree/bindings/media/mediatek-vpu.txt for details. - -Required properties (all function blocks, child node): -- compatible: Should be one of - "mediatek,mt8173-mdp-rdma" - read DMA - "mediatek,mt8173-mdp-rsz" - resizer - "mediatek,mt8173-mdp-wdma" - write DMA - "mediatek,mt8173-mdp-wrot" - write DMA with rotation -- reg: Physical base address and length of the function block register space -- clocks: device clocks, see - Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- power-domains: a phandle to the power domain, see - Documentation/devicetree/bindings/power/power_domain.txt for details. - -Required properties (DMA function blocks, child node): -- compatible: Should be one of - "mediatek,mt8173-mdp-rdma" - "mediatek,mt8173-mdp-wdma" - "mediatek,mt8173-mdp-wrot" -- iommus: should point to the respective IOMMU block with master port as - argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml - for details. - -Example: - mdp_rdma0: rdma@14001000 { - compatible = "mediatek,mt8173-mdp-rdma"; - "mediatek,mt8173-mdp"; - reg = <0 0x14001000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RDMA0>, - <&mmsys CLK_MM_MUTEX_32K>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_RDMA0>; - mediatek,vpu = <&vpu>; - }; - - mdp_rdma1: rdma@14002000 { - compatible = "mediatek,mt8173-mdp-rdma"; - reg = <0 0x14002000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RDMA1>, - <&mmsys CLK_MM_MUTEX_32K>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_RDMA1>; - }; - - mdp_rsz0: rsz@14003000 { - compatible = "mediatek,mt8173-mdp-rsz"; - reg = <0 0x14003000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RSZ0>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - }; - - mdp_rsz1: rsz@14004000 { - compatible = "mediatek,mt8173-mdp-rsz"; - reg = <0 0x14004000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RSZ1>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - }; - - mdp_rsz2: rsz@14005000 { - compatible = "mediatek,mt8173-mdp-rsz"; - reg = <0 0x14005000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RSZ2>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - }; - - mdp_wdma0: wdma@14006000 { - compatible = "mediatek,mt8173-mdp-wdma"; - reg = <0 0x14006000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_WDMA>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_WDMA>; - }; - - mdp_wrot0: wrot@14007000 { - compatible = "mediatek,mt8173-mdp-wrot"; - reg = <0 0x14007000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_WROT0>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_WROT0>; - }; - - mdp_wrot1: wrot@14008000 { - compatible = "mediatek,mt8173-mdp-wrot"; - reg = <0 0x14008000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_WROT1>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_WROT1>; - }; -- 2.50.1 Convert the existing text-based DT bindings for Mediatek MT8173 Video Processor Unit to a YAML schema. Signed-off-by: Ariel D'Alessandro --- .../bindings/media/mediatek,mt8173-vpu.yaml | 76 +++++++++++++++++++ .../bindings/media/mediatek-vpu.txt | 31 -------- 2 files changed, 76 insertions(+), 31 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml delete mode 100644 Documentation/devicetree/bindings/media/mediatek-vpu.txt diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml new file mode 100644 index 0000000000000..44f5d7cc44042 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mt8173-vpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8173 Video Processor Unit + +maintainers: + - Ariel D'Alessandro + +description: + Video Processor Unit is a HW video controller. It controls HW Codec including + H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color convert). + +properties: + compatible: + const: mediatek,mt8173-vpu + + reg: + minItems: 2 + + reg-names: + items: + - const: tcm + - const: cfg_reg + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: main + + memory-region: + description: + phandle to a node describing reserved memory used by VPU + (see bindings/reserved-memory/reserved-memory.txt) + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + - memory-region + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + vpu: vpu@10020000 { + compatible = "mediatek,mt8173-vpu"; + reg = <0 0x10020000 0 0x30000>, + <0 0x10050000 0 0x100>; + reg-names = "tcm", "cfg_reg"; + interrupts = ; + clocks = <&topckgen CLK_TOP_SCP_SEL>; + clock-names = "main"; + memory-region = <&vpu_dma_reserved>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/media/mediatek-vpu.txt b/Documentation/devicetree/bindings/media/mediatek-vpu.txt deleted file mode 100644 index 2a5bac37f9a22..0000000000000 --- a/Documentation/devicetree/bindings/media/mediatek-vpu.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Mediatek Video Processor Unit - -Video Processor Unit is a HW video controller. It controls HW Codec including -H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color convert). - -Required properties: - - compatible: "mediatek,mt8173-vpu" - - reg: Must contain an entry for each entry in reg-names. - - reg-names: Must include the following entries: - "tcm": tcm base - "cfg_reg": Main configuration registers base - - interrupts: interrupt number to the cpu. - - clocks : clock name from clock manager - - clock-names: must be main. It is the main clock of VPU - -Optional properties: - - memory-region: phandle to a node describing memory (see - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) - to be used for VPU extended memory; if not present, VPU may be located - anywhere in the memory - -Example: - vpu: vpu@10020000 { - compatible = "mediatek,mt8173-vpu"; - reg = <0 0x10020000 0 0x30000>, - <0 0x10050000 0 0x100>; - reg-names = "tcm", "cfg_reg"; - interrupts = ; - clocks = <&topckgen TOP_SCP_SEL>; - clock-names = "main"; - }; -- 2.50.1 Current, the DT bindings for MediaTek mmsys controller is missing the assigned-clocks and assigned-clocks-rates properties. Add these and update the example as well. Signed-off-by: Ariel D'Alessandro --- .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 3f4262e93c789..d045d366eb8e2 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -68,6 +68,12 @@ properties: of the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for details. + assigned-clocks: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + mboxes: description: Using mailbox to communicate with GCE, it should have this @@ -130,6 +136,7 @@ additionalProperties: false examples: - | + #include #include #include @@ -137,6 +144,8 @@ examples: compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0x14000000 0x1000>; power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; + assigned-clock-rates = <400000000>; #clock-cells = <1>; #reset-cells = <1>; mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, -- 2.50.1 Convert the existing text-based DT bindings for Marvell 8897/8997 (sd8897/sd8997) bluetooth devices controller to a YAML schema. While here, bindings for "usb1286,204e" (USB interface) are dropped from the YAML definition as these are currently documented in file: - Documentation/devicetree/bindings/net/btusb.txt Signed-off-by: Ariel D'Alessandro --- .../bindings/net/marvell,sd8897-bt.yaml | 91 +++++++++++++++++++ .../bindings/net/marvell-bt-8xxx.txt | 83 ----------------- 2 files changed, 91 insertions(+), 83 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/marvell,sd8897-bt.yaml delete mode 100644 Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt diff --git a/Documentation/devicetree/bindings/net/marvell,sd8897-bt.yaml b/Documentation/devicetree/bindings/net/marvell,sd8897-bt.yaml new file mode 100644 index 0000000000000..6539868c08b8a --- /dev/null +++ b/Documentation/devicetree/bindings/net/marvell,sd8897-bt.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/marvell,sd8897-bt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell 8897/8997 (sd8897/sd8997) bluetooth devices (SDIO) + +maintainers: + - Ariel D'Alessandro + +properties: + compatible: + enum: + - marvell,sd8897-bt + - marvell,sd8997-bt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + marvell,cal-data: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: + Calibration data downloaded to the device during initialization. + minItems: 28 + + marvell,wakeup-pin: + $ref: /schemas/types.yaml#/definitions/uint16 + description: + Wakeup pin number of the bluetooth chip. Used by firmware to wakeup host + system. + + marvell,wakeup-gap-ms: + description: + Wakeup latency of the host platform. Required by the chip sleep feature. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + sdio0 { + #address-cells = <1>; + #size-cells = <0>; + + btmrvl: btmrvl@2 { + compatible = "marvell,sd8897-bt"; + reg = <2>; + interrupt-parent = <&gpio4>; + interrupts = ; + marvell,wakeup-pin = /bits/ 16 <13>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l>; + }; + }; + + mmc3 { + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + + bluetooth: bluetooth@2 { + compatible = "marvell,sd8897-bt"; + reg = <2>; + interrupt-parent = <&pio>; + interrupts = <119 IRQ_TYPE_LEVEL_LOW>; + + marvell,cal-data = /bits/ 8 < + 0x37 0x01 0x1c 0x00 0xff 0xff 0xff 0xff 0x01 0x7f 0x04 0x02 + 0x00 0x00 0xba 0xce 0xc0 0xc6 0x2d 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0xf0 0x00>; + marvell,wakeup-pin = /bits/ 16 <0x0d>; + marvell,wakeup-gap-ms = /bits/ 16 <0x64>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt b/Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt deleted file mode 100644 index 957e5e5c2927c..0000000000000 --- a/Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt +++ /dev/null @@ -1,83 +0,0 @@ -Marvell 8897/8997 (sd8897/sd8997) bluetooth devices (SDIO or USB based) ------- -The 8997 devices supports multiple interfaces. When used on SDIO interfaces, -the btmrvl driver is used and when used on USB interface, the btusb driver is -used. - -Required properties: - - - compatible : should be one of the following: - * "marvell,sd8897-bt" (for SDIO) - * "marvell,sd8997-bt" (for SDIO) - * "usb1286,204e" (for USB) - -Optional properties: - - - marvell,cal-data: Calibration data downloaded to the device during - initialization. This is an array of 28 values(u8). - This is only applicable to SDIO devices. - - - marvell,wakeup-pin: It represents wakeup pin number of the bluetooth chip. - firmware will use the pin to wakeup host system (u16). - - marvell,wakeup-gap-ms: wakeup gap represents wakeup latency of the host - platform. The value will be configured to firmware. This - is needed to work chip's sleep feature as expected (u16). - - interrupt-names: Used only for USB based devices (See below) - - interrupts : specifies the interrupt pin number to the cpu. For SDIO, the - driver will use the first interrupt specified in the interrupt - array. For USB based devices, the driver will use the interrupt - named "wakeup" from the interrupt-names and interrupt arrays. - The driver will request an irq based on this interrupt number. - During system suspend, the irq will be enabled so that the - bluetooth chip can wakeup host platform under certain - conditions. During system resume, the irq will be disabled - to make sure unnecessary interrupt is not received. - -Example: - -IRQ pin 119 is used as system wakeup source interrupt. -wakeup pin 13 and gap 100ms are configured so that firmware can wakeup host -using this device side pin and wakeup latency. - -Example for SDIO device follows (calibration data is also available in -below example). - -&mmc3 { - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - btmrvl: bluetooth@2 { - compatible = "marvell,sd8897-bt"; - reg = <2>; - interrupt-parent = <&pio>; - interrupts = <119 IRQ_TYPE_LEVEL_LOW>; - - marvell,cal-data = /bits/ 8 < - 0x37 0x01 0x1c 0x00 0xff 0xff 0xff 0xff 0x01 0x7f 0x04 0x02 - 0x00 0x00 0xba 0xce 0xc0 0xc6 0x2d 0x00 0x00 0x00 0x00 0x00 - 0x00 0x00 0xf0 0x00>; - marvell,wakeup-pin = /bits/ 16 <0x0d>; - marvell,wakeup-gap-ms = /bits/ 16 <0x64>; - }; -}; - -Example for USB device: - -&usb_host1_ohci { - #address-cells = <1>; - #size-cells = <0>; - - mvl_bt1: bt@1 { - compatible = "usb1286,204e"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupt-names = "wakeup"; - interrupts = <119 IRQ_TYPE_LEVEL_LOW>; - marvell,wakeup-pin = /bits/ 16 <0x0d>; - marvell,wakeup-gap-ms = /bits/ 16 <0x64>; - }; -}; -- 2.50.1 Convert the existing text-based DT bindings for Mediatek MT8173 RT5650 codecs to a YAML schema. Signed-off-by: Ariel D'Alessandro --- .../sound/mediatek,mt8173-rt5650.yaml | 73 +++++++++++++++++++ .../bindings/sound/mt8173-rt5650.txt | 31 -------- 2 files changed, 73 insertions(+), 31 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt8173-rt5650.yaml delete mode 100644 Documentation/devicetree/bindings/sound/mt8173-rt5650.txt diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8173-rt5650.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8173-rt5650.yaml new file mode 100644 index 0000000000000..36e4f9c4c3d62 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8173-rt5650.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8173-rt5650.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8173 with RT5650 codecs and HDMI via I2S + +maintainers: + - Ariel D'Alessandro + +properties: + compatible: + const: "mediatek,mt8173-rt5650" + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + mediatek,audio-codec: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + The phandles of rt5650 codecs and of the HDMI encoder node. + minItems: 2 + + mediatek,platform: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of MT8173 ASoC platform. + + mediatek,mclk: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The MCLK source. + 0: external oscillator, MCLK = 12.288M + 1: internal source from mt8173, MCLK = sampling rate * 256 + + codec-capture: + description: Subnode of rt5650 codec capture. + type: object + + properties: + sound-dai: + maxItems: 1 + description: phandle of the CPU DAI + + additionalProperties: false + +required: + - compatible + - mediatek,audio-codec + - mediatek,platform + +additionalProperties: false + +examples: + - | + sound: sound { + compatible = "mediatek,mt8173-rt5650"; + mediatek,audio-codec = <&rt5650 &hdmi0>; + mediatek,platform = <&afe>; + pinctrl-names = "default"; + pinctrl-0 = <&aud_i2s2>; + + mediatek,mclk = <1>; + codec-capture { + sound-dai = <&rt5650 1>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/mt8173-rt5650.txt b/Documentation/devicetree/bindings/sound/mt8173-rt5650.txt deleted file mode 100644 index 29dce2ac8773a..0000000000000 --- a/Documentation/devicetree/bindings/sound/mt8173-rt5650.txt +++ /dev/null @@ -1,31 +0,0 @@ -MT8173 with RT5650 CODECS and HDMI via I2S - -Required properties: -- compatible : "mediatek,mt8173-rt5650" -- mediatek,audio-codec: the phandles of rt5650 codecs - and of the hdmi encoder node -- mediatek,platform: the phandle of MT8173 ASoC platform - -Optional subnodes: -- codec-capture : the subnode of rt5650 codec capture -Required codec-capture subnode properties: -- sound-dai: audio codec dai name on capture path - <&rt5650 0> : Default setting. Connect rt5650 I2S1 for capture. (dai_name = rt5645-aif1) - <&rt5650 1> : Connect rt5650 I2S2 for capture. (dai_name = rt5645-aif2) - -- mediatek,mclk: the MCLK source - 0 : external oscillator, MCLK = 12.288M - 1 : internal source from mt8173, MCLK = sampling rate*256 - -Example: - - sound { - compatible = "mediatek,mt8173-rt5650"; - mediatek,audio-codec = <&rt5650 &hdmi0>; - mediatek,platform = <&afe>; - mediatek,mclk = <0>; - codec-capture { - sound-dai = <&rt5650 1>; - }; - }; - -- 2.50.1 Current, the DT bindings for Mediatek OD (display overdrive) is missing the mediatek,gce-client-reg property. Add it and update the example as well. Signed-off-by: Ariel D'Alessandro --- .../bindings/display/mediatek/mediatek,od.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml index 71534febd49c6..d5b42a4bba190 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml @@ -60,6 +60,14 @@ properties: - port@0 - port@1 + mediatek,gce-client-reg: + description: The register of client driver can be configured by gce with + 4 arguments defined in this property, such as phandle of gce, subsys id, + register offset and size. Each GCE subsys id is mapping to a client + defined in the header include/dt-bindings/gce/-gce.h. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + required: - compatible - reg @@ -70,6 +78,7 @@ additionalProperties: false examples: - | #include + #include soc { #address-cells = <2>; @@ -79,5 +88,6 @@ examples: compatible = "mediatek,mt8173-disp-od"; reg = <0 0x14023000 0 0x1000>; clocks = <&mmsys CLK_MM_DISP_OD>; + mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; }; }; -- 2.50.1 Current, the DT bindings for Mediatek UFOe (Unified Frame Optimization engine) is missing the mediatek,gce-client-reg property. Add it and update the example as well. Signed-off-by: Ariel D'Alessandro --- .../bindings/display/mediatek/mediatek,ufoe.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml index 61a5e22effbf2..ecb4c0359fec3 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml @@ -64,6 +64,14 @@ properties: - port@0 - port@1 + mediatek,gce-client-reg: + description: The register of client driver can be configured by gce with + 4 arguments defined in this property, such as phandle of gce, subsys id, + register offset and size. Each GCE subsys id is mapping to a client + defined in the header include/dt-bindings/gce/-gce.h. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + required: - compatible - reg @@ -77,7 +85,9 @@ examples: - | #include #include + #include #include + soc { #address-cells = <2>; #size-cells = <2>; @@ -88,5 +98,6 @@ examples: interrupts = ; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_UFOE>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; }; }; -- 2.50.1 According to the mediatek,mt8173-pinctrl device tree binding schema, the pinctrl node names should match pattern 'pins$'. Fix this. Signed-off-by: Ariel D'Alessandro --- .../boot/dts/mediatek/mt8173-elm-hana.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 26 +++++++++---------- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 14 +++++----- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 14 +++++----- 4 files changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi index dfc5c2f0ddefd..7d665cedf8a44 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi @@ -80,7 +80,7 @@ pins2 { }; }; - mmc1_pins_default: mmc1default { + mmc1_pins_default: mmc1_default_pins { pins_wp { pinmux = ; input-enable; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 0d995b342d463..0766026864c9d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -601,7 +601,7 @@ &pio { "SOC_I2C4_1V8_SDA_400K", "SOC_I2C4_1V8_SCL_400K"; - aud_i2s2: aud_i2s2 { + aud_i2s2: aud_i2s2_pins { pins1 { pinmux = , , @@ -654,14 +654,14 @@ pins1 { }; }; - i2c1_pins_a: i2c1 { + i2c1_pins_a: i2c1_pins { da9211_pins { pinmux = ; bias-pull-up; }; }; - mmc0_pins_default: mmc0default { + mmc0_pins_default: mmc0_default_pins { pins_cmd_dat { pinmux = , , @@ -686,7 +686,7 @@ pins_rst { }; }; - mmc1_pins_default: mmc1default { + mmc1_pins_default: mmc1_default_pins { pins_cmd_dat { pinmux = , , @@ -710,7 +710,7 @@ pins_insert { }; }; - mmc3_pins_default: mmc3default { + mmc3_pins_default: mmc3_default_pins { pins_dat { pinmux = , , @@ -735,7 +735,7 @@ pins_clk { }; }; - mmc0_pins_uhs: mmc0 { + mmc0_pins_uhs: mmc0_uhs_pins { pins_cmd_dat { pinmux = , , @@ -769,7 +769,7 @@ pins_rst { }; }; - mmc1_pins_uhs: mmc1 { + mmc1_pins_uhs: mmc1_uhs_pins { pins_cmd_dat { pinmux = , , @@ -788,7 +788,7 @@ pins_clk { }; }; - mmc3_pins_uhs: mmc3 { + mmc3_pins_uhs: mmc3_uhs_pins { pins_dat { pinmux = , , @@ -813,7 +813,7 @@ pins_clk { }; }; - nor_gpio1_pins: nor { + nor_gpio1_pins: nor_pins { pins1 { pinmux = , , @@ -863,7 +863,7 @@ pins1 { }; }; - rt5650_irq: rt5650_irq { + rt5650_irq: rt5650_irq_pins { pins1 { pinmux = ; bias-pull-down; @@ -877,7 +877,7 @@ pins1 { }; }; - spi_pins_a: spi1 { + spi_pins_a: spi1_pins { pins1 { pinmux = ; bias-pull-up; @@ -892,7 +892,7 @@ pins_spi { }; }; - trackpad_irq: trackpad_irq { + trackpad_irq: trackpad_irq_pins { pins1 { pinmux = ; input-enable; @@ -900,7 +900,7 @@ pins1 { }; }; - usb_pins: usb { + usb_pins: usb_pins { pins1 { pinmux = ; output-high; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 9fffed0ef4bff..f28110c331c71 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -179,7 +179,7 @@ pins1 { }; }; - mmc0_pins_default: mmc0default { + mmc0_pins_default: mmc0_default_pins { pins_cmd_dat { pinmux = , , @@ -205,7 +205,7 @@ pins_rst { }; }; - mmc1_pins_default: mmc1default { + mmc1_pins_default: mmc1_default_pins { pins_cmd_dat { pinmux = , , @@ -229,7 +229,7 @@ pins_insert { }; }; - mmc0_pins_uhs: mmc0 { + mmc0_pins_uhs: mmc0_uhs_pins { pins_cmd_dat { pinmux = , , @@ -257,7 +257,7 @@ pins_rst { }; }; - mmc1_pins_uhs: mmc1 { + mmc1_pins_uhs: mmc1_uhs_pins { pins_cmd_dat { pinmux = , , @@ -276,14 +276,14 @@ pins_clk { }; }; - usb_id_pins_float: usb_iddig_pull_up { + usb_id_pins_float: usb_iddig_pull_up_pins { pins_iddig { pinmux = ; bias-pull-up; }; }; - usb_id_pins_ground: usb_iddig_pull_down { + usb_id_pins_ground: usb_iddig_pull_down_pins { pins_iddig { pinmux = ; bias-pull-down; @@ -474,7 +474,7 @@ mt6397_vibr_reg: ldo_vibr { }; &pio { - spi_pins_a: spi0 { + spi_pins_a: spi0_pins { pins_spi { pinmux = , , diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 122a57c3780b6..7e522bb8963a0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -391,7 +391,7 @@ pio: pinctrl@1000b000 { , ; - hdmi_pin: xxx { + hdmi_pin: hdmi_pins { /*hdmi htplg pin*/ pins1 { @@ -401,7 +401,7 @@ pins1 { }; }; - i2c0_pins_a: i2c0 { + i2c0_pins_a: i2c0_pins { pins1 { pinmux = , ; @@ -409,7 +409,7 @@ pins1 { }; }; - i2c1_pins_a: i2c1 { + i2c1_pins_a: i2c1_pins { pins1 { pinmux = , ; @@ -417,7 +417,7 @@ pins1 { }; }; - i2c2_pins_a: i2c2 { + i2c2_pins_a: i2c2_pins { pins1 { pinmux = , ; @@ -425,7 +425,7 @@ pins1 { }; }; - i2c3_pins_a: i2c3 { + i2c3_pins_a: i2c3_pins { pins1 { pinmux = , ; @@ -433,7 +433,7 @@ pins1 { }; }; - i2c4_pins_a: i2c4 { + i2c4_pins_a: i2c4_pins { pins1 { pinmux = , ; @@ -441,7 +441,7 @@ pins1 { }; }; - i2c6_pins_a: i2c6 { + i2c6_pins_a: i2c6_pins { pins1 { pinmux = , ; -- 2.50.1 Current, the DT bindings for MediaTek's MT65xx Pin controller is missing the gpio-line-names property, add it to the associated schema. Signed-off-by: Ariel D'Alessandro --- .../devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index b9680b896f12f..aa71398cf522f 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -43,6 +43,8 @@ properties: the amount of cells must be specified as 2. See the below mentioned gpio binding representation for description of particular cells. + gpio-line-names: true + mediatek,pctl-regmap: $ref: /schemas/types.yaml#/definitions/phandle-array items: -- 2.50.1 Convert the existing text-based DT bindings for Dialog Semiconductor DA9211 Voltage Regulators family to a YAML schema. Examples are simplified, as these are all equal. Signed-off-by: Ariel D'Alessandro --- .../devicetree/bindings/regulator/da9211.txt | 205 ------------------ .../bindings/regulator/dlg,da9211.yaml | 104 +++++++++ 2 files changed, 104 insertions(+), 205 deletions(-) delete mode 100644 Documentation/devicetree/bindings/regulator/da9211.txt create mode 100644 Documentation/devicetree/bindings/regulator/dlg,da9211.yaml diff --git a/Documentation/devicetree/bindings/regulator/da9211.txt b/Documentation/devicetree/bindings/regulator/da9211.txt deleted file mode 100644 index eb871447d5082..0000000000000 --- a/Documentation/devicetree/bindings/regulator/da9211.txt +++ /dev/null @@ -1,205 +0,0 @@ -* Dialog Semiconductor DA9211/DA9212/DA9213/DA9223/DA9214/DA9224/DA9215/DA9225 - Voltage Regulator - -Required properties: -- compatible: "dlg,da9211" or "dlg,da9212" or "dlg,da9213" or "dlg,da9223" - or "dlg,da9214" or "dlg,da9224" or "dlg,da9215" or "dlg,da9225" -- reg: I2C slave address, usually 0x68. -- interrupts: the interrupt outputs of the controller -- regulators: A node that houses a sub-node for each regulator within the - device. Each sub-node is identified using the node's name, with valid - values listed below. The content of each sub-node is defined by the - standard binding for regulators; see regulator.txt. - BUCKA and BUCKB. - -Optional properties: -- enable-gpios: platform gpio for control of BUCKA/BUCKB. -- Any optional property defined in regulator.txt - - regulator-initial-mode and regulator-allowed-modes may be specified using - mode values from dt-bindings/regulator/dlg,da9211-regulator.h - -Example 1) DA9211 - pmic: da9211@68 { - compatible = "dlg,da9211"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <5000000>; - enable-gpios = <&gpio 27 0>; - regulator-allowed-modes = ; - }; - }; - }; - -Example 2) DA9212 - pmic: da9212@68 { - compatible = "dlg,da9212"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <5000000>; - enable-gpios = <&gpio 27 0>; - }; - BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <5000000>; - enable-gpios = <&gpio 17 0>; - }; - }; - }; - -Example 3) DA9213 - pmic: da9213@68 { - compatible = "dlg,da9213"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 27 0>; - }; - }; - }; - -Example 4) DA9223 - pmic: da9223@68 { - compatible = "dlg,da9223"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 27 0>; - }; - }; - }; - -Example 5) DA9214 - pmic: da9214@68 { - compatible = "dlg,da9214"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 27 0>; - }; - BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 17 0>; - }; - }; - }; - -Example 6) DA9224 - pmic: da9224@68 { - compatible = "dlg,da9224"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 27 0>; - }; - BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 17 0>; - }; - }; - }; - -Example 7) DA9215 - pmic: da9215@68 { - compatible = "dlg,da9215"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <4000000>; - regulator-max-microamp = <7000000>; - enable-gpios = <&gpio 27 0>; - }; - BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <4000000>; - regulator-max-microamp = <7000000>; - enable-gpios = <&gpio 17 0>; - }; - }; - }; - -Example 8) DA9225 - pmic: da9225@68 { - compatible = "dlg,da9225"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <4000000>; - regulator-max-microamp = <7000000>; - enable-gpios = <&gpio 27 0>; - }; - BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <4000000>; - regulator-max-microamp = <7000000>; - enable-gpios = <&gpio 17 0>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/dlg,da9211.yaml b/Documentation/devicetree/bindings/regulator/dlg,da9211.yaml new file mode 100644 index 0000000000000..d4c5b354497f4 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/dlg,da9211.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/dlg,da9211.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: | + Dialog Semiconductor DA9211/DA9212/DA9213/DA9223/DA9214/DA9224/DA9215/DA9225 + Voltage Regulator + +maintainers: + - Ariel D'Alessandro + +properties: + compatible: + enum: + - "dlg,da9211" + - "dlg,da9212" + - "dlg,da9213" + - "dlg,da9223" + - "dlg,da9214" + - "dlg,da9224" + - "dlg,da9215" + - "dlg,da9225" + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + regulators: + type: object + additionalProperties: false + description: | + List of regulators provided by the device + + patternProperties: + "^BUCK([A-B])$": + type: object + $ref: regulator.yaml# + description: | + Properties for a single BUCK regulator + + properties: + regulator-initial-mode: + items: + enum: [ 1, 2, 3 ] + description: Defined in include/dt-bindings/regulator/dlg,da9211-regulator.h + + regulator-allowed-modes: + items: + enum: [ 1, 2, 3 ] + description: Defined in include/dt-bindings/regulator/dlg,da9211-regulator.h + + enable-gpios: + maxItems: 1 + description: Specify a valid GPIO for platform control of the regulator + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - regulators + +additionalProperties: false + +examples: + - | + #include + + i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + da9212: da9212@68 { + compatible = "dlg,da9212"; + reg = <0x68>; + interrupts = <3 27>; + + regulators { + BUCKA { + regulator-name = "VBUCKA"; + regulator-min-microvolt = < 300000>; + regulator-max-microvolt = <1570000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <5000000>; + enable-gpios = <&gpio 27 0>; + }; + BUCKB { + regulator-name = "VBUCKB"; + regulator-min-microvolt = < 300000>; + regulator-max-microvolt = <1570000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <5000000>; + enable-gpios = <&gpio 17 0>; + }; + }; + }; + }; + +... -- 2.50.1 The mediatek,mt8173-thermal device tree binding schema doesn't allow regulator supplies like the ones defined in mt8173-elm.dtsi. Drop these as the associated driver doesn't implement them either. Signed-off-by: Ariel D'Alessandro --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 0766026864c9d..b6fe979fcfb10 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -1149,11 +1149,6 @@ &ssusb { status = "okay"; }; -&thermal { - bank0-supply = <&mt6397_vpca15_reg>; - bank1-supply = <&da9211_vcpu_reg>; -}; - &uart0 { status = "okay"; }; -- 2.50.1 Currently, the DT bindings for Mediatek PMIC Wrapper is missing the power-domains property, which is used in the MT8173 E1 evaluation board as it needs USB power domain. Signed-off-by: Ariel D'Alessandro --- .../bindings/soc/mediatek/mediatek,pwrap.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml index 4737e5f45d541..54c0cd64d3094 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml @@ -98,6 +98,9 @@ properties: - const: pwrap - const: pwrap-bridge + power-domains: + maxItems: 1 + pmic: type: object @@ -126,6 +129,18 @@ allOf: clock-names: minItems: 4 + - if: + properties: + compatible: + contains: + const: mediatek,mt8173-pwrap + then: + properties: + power-domains: true + else: + properties: + power-domains: false + additionalProperties: false examples: -- 2.50.1 Convert the existing text-based DT bindings for MELFAS MIP4 Touchscreen controller to a YAML schema. Signed-off-by: Ariel D'Alessandro --- .../input/touchscreen/melfas,mip4_ts.yaml | 55 +++++++++++++++++++ .../input/touchscreen/melfas_mip4.txt | 20 ------- 2 files changed, 55 insertions(+), 20 deletions(-) create mode 100644 Documentation/devicetree/bindings/input/touchscreen/melfas,mip4_ts.yaml delete mode 100644 Documentation/devicetree/bindings/input/touchscreen/melfas_mip4.txt diff --git a/Documentation/devicetree/bindings/input/touchscreen/melfas,mip4_ts.yaml b/Documentation/devicetree/bindings/input/touchscreen/melfas,mip4_ts.yaml new file mode 100644 index 0000000000000..170fd4212467e --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/melfas,mip4_ts.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/melfas,mip4_ts.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MELFAS MIP4 Touchscreen + +maintainers: + - Ariel D'Alessandro + +properties: + compatible: + const: "melfas,mip4_ts" + + reg: + description: I2C address of the chip (0x48 or 0x34) + maxItems: 1 + + interrupts: + maxItems: 1 + + ce-gpios: + description: GPIO connected to the CE (chip enable) pin of the chip + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@34 { + compatible = "melfas,mip4_ts"; + reg = <0x34>; + + interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; + ce-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&touchscreen_default>; + pinctrl-names = "default"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/input/touchscreen/melfas_mip4.txt b/Documentation/devicetree/bindings/input/touchscreen/melfas_mip4.txt deleted file mode 100644 index b2ab5498e5190..0000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/melfas_mip4.txt +++ /dev/null @@ -1,20 +0,0 @@ -* MELFAS MIP4 Touchscreen - -Required properties: -- compatible: must be "melfas,mip4_ts" -- reg: I2C slave address of the chip (0x48 or 0x34) -- interrupts: interrupt to which the chip is connected - -Optional properties: -- ce-gpios: GPIO connected to the CE (chip enable) pin of the chip - -Example: - i2c@00000000 { - touchscreen: melfas_mip4@48 { - compatible = "melfas,mip4_ts"; - reg = <0x48>; - interrupt-parent = <&gpio>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - ce-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; - }; - }; -- 2.50.1 Commit 14176e94bb35d ("arm64: dts: mediatek: mt8195: Fix ranges for jpeg enc/decoder nodes") redefined jpeg encoder/decoder children node ranges. Update the related device tree binding yaml definition to match mediatek/mt8195.dtsi, as this is currently the only one using it. Signed-off-by: Ariel D'Alessandro --- .../media/mediatek,mt8195-jpegdec.yaml | 31 ++++++++++--------- .../media/mediatek,mt8195-jpegenc.yaml | 15 ++++----- 2 files changed, 24 insertions(+), 22 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml index e5448c60e3eb5..b1f3df258dc87 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml @@ -36,7 +36,7 @@ properties: # Required child node: patternProperties: - "^jpgdec@[0-9a-f]+$": + "^jpgdec@[0-9],[0-9a-f]+$": type: object description: The jpeg decoder hardware device node which should be added as subnodes to @@ -100,22 +100,23 @@ examples: #address-cells = <2>; #size-cells = <2>; - jpgdec-master { + jpeg-decoder@1a040000 { compatible = "mediatek,mt8195-jpgdec"; power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; - iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>, - <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>, - <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>, - <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>, - <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, - <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; + iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0 0 0 0x1a040000 0 0x20000>, + <1 0 0 0x1b040000 0 0x10000>; - jpgdec@1a040000 { + jpgdec@0,0 { compatible = "mediatek,mt8195-jpgdec-hw"; - reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ + reg = <0 0 0 0x10000>;/* JPGDEC_C0 */ iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, @@ -128,9 +129,9 @@ examples: power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; }; - jpgdec@1a050000 { + jpgdec@0,10000 { compatible = "mediatek,mt8195-jpgdec-hw"; - reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ + reg = <0 0 0x10000 0x10000>;/* JPGDEC_C1 */ iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, @@ -143,9 +144,9 @@ examples: power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; }; - jpgdec@1b040000 { + jpgdec@1,0 { compatible = "mediatek,mt8195-jpgdec-hw"; - reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ + reg = <1 0 0 0x10000>;/* JPGDEC_C2 */ iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml index 596186497b684..190e4e7470195 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml @@ -36,7 +36,7 @@ properties: # Required child node: patternProperties: - "^jpgenc@[0-9a-f]+$": + "^jpgenc@[0-9],[0-9a-f]+$": type: object description: The jpeg encoder hardware device node which should be added as subnodes to @@ -100,7 +100,7 @@ examples: #address-cells = <2>; #size-cells = <2>; - jpgenc-master { + jpeg-encoder@1a030000 { compatible = "mediatek,mt8195-jpgenc"; power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, @@ -109,11 +109,12 @@ examples: <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0 0 0 0x1a030000 0 0x10000>, + <1 0 0 0x1b030000 0 0x10000>; - jpgenc@1a030000 { + jpgenc@0,0 { compatible = "mediatek,mt8195-jpgenc-hw"; - reg = <0 0x1a030000 0 0x10000>; + reg = <0 0 0 0x10000>; iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, @@ -124,9 +125,9 @@ examples: power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; }; - jpgenc@1b030000 { + jpgenc@1,0 { compatible = "mediatek,mt8195-jpgenc-hw"; - reg = <0 0x1b030000 0 0x10000>; + reg = <1 0 0 0x10000>; iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, -- 2.50.1