The DLL is a Qualcomm-specific hardware component integrated within the MAC and should be configured in bypass mode for 10 Mbps and 100 Mbps speeds. If not bypassed, the timing delay will be incorrectly applied, which will disrupt signal sampling. Fixes: a7c30e62d4b8 ("net: stmmac: Add driver for Qualcomm ethqos") Signed-off-by: Yijie Yang --- drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index d8fd4d8f6ced..a4ea72f86ca8 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -64,6 +64,9 @@ #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1) #define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0) +/* SDCC_USR_CTL fields */ +#define SDCC_USR_CTL_DLL_BYPASS BIT(30) + /* SDC4_STATUS bits */ #define SDC4_STATUS_DLL_LOCK BIT(7) @@ -609,6 +612,17 @@ static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos, int speed) if (speed == SPEED_1000) ethqos_dll_configure(ethqos); + /* The DLL (Delay Locked Loop) aligns the clock and samples data + * in RGMII interfaces. It should be bypassed for 10 Mbps and + * 100 Mbps speeds. + */ + if (speed == SPEED_10 || speed == SPEED_100) { + rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, SDCC_DLL_CONFIG_PDN, + SDCC_HC_REG_DLL_CONFIG); + rgmii_updatel(ethqos, SDCC_USR_CTL_DLL_BYPASS, + SDCC_USR_CTL_DLL_BYPASS, SDCC_USR_CTL); + } + ethqos_rgmii_macro_init(ethqos, speed); return 0; -- 2.34.1 In the initial device tree submission, the definitions of rgmii and rgmii-id in the phy-mode property were inverted compared to the conventions used by the upstream Linux kernel community. Only QCS-EVB-400 and SA8155-ADP platforms are affected due to the incorrect PHY mode configuration: 'rgmii' was used instead of the correct 'rgmii-id'. This change results in an ABI compatibility break, but it is acceptable as these platforms are not actively used by any customers, based on current observations. Qualcomm expects the MAC, not the PHY, to introduce the timing delay, and the driver is designed accordingly. This is due to specific SoC hardware that handles delay and sampling internally. Signed-off-by: Yijie Yang --- drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index a4ea72f86ca8..a3e595e3b1e4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -390,14 +390,11 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos) static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed) { struct device *dev = ðqos->pdev->dev; - int phase_shift; + int phase_shift = 0; int loopback; /* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */ - if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID || - ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID) - phase_shift = 0; - else + if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID) phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN; /* Disable loopback mode */ @@ -803,7 +800,14 @@ static int qcom_ethqos_probe(struct platform_device *pdev) if (!ethqos) return -ENOMEM; + /* Qualcomm configures the MAC to introduce delay; instruct the + * PHY not to add additional delay. + */ + if (plat_dat->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) + plat_dat->phy_interface = PHY_INTERFACE_MODE_RGMII; + ethqos->phy_mode = plat_dat->phy_interface; + switch (ethqos->phy_mode) { case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: -- 2.34.1 From: Yijie Yang Add an ethernet controller node for QCS615 SoC to enable ethernet functionality. Reviewed-by: Konrad Dybcio Signed-off-by: Yijie Yang --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi index 591fcb740259..8ec97532911c 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -491,6 +491,39 @@ soc: soc@0 { dma-ranges = <0 0 0 0 0x10 0>; #address-cells = <2>; #size-cells = <2>; + ethernet: ethernet@20000 { + compatible = "qcom,qcs615-ethqos", "qcom,qcs404-ethqos"; + reg = <0x0 0x00020000 0x0 0x10000>, + <0x0 0x00036000 0x0 0x100>; + reg-names = "stmmaceth", + "rgmii"; + + clocks = <&gcc GCC_EMAC_AXI_CLK>, + <&gcc GCC_EMAC_SLV_AHB_CLK>, + <&gcc GCC_EMAC_PTP_CLK>, + <&gcc GCC_EMAC_RGMII_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "rgmii"; + + interrupts = , + ; + interrupt-names = "macirq", + "eth_lpi"; + + power-domains = <&gcc EMAC_GDSC>; + resets = <&gcc GCC_EMAC_BCR>; + + iommus = <&apps_smmu 0x1c0 0x0>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <20480>; + + status = "disabled"; + }; gcc: clock-controller@100000 { compatible = "qcom,qcs615-gcc"; -- 2.34.1 From: Yijie Yang Enable the ethernet node, add the phy node and pinctrl for ethernet. Reviewed-by: Konrad Dybcio Signed-off-by: Yijie Yang --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 104 +++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 59582d3dc4c4..05d8609c0483 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -288,6 +288,59 @@ vreg_l17a: ldo17 { }; }; +ðernet { + pinctrl-0 = <ðernet_defaults>; + pinctrl-names = "default"; + + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + status = "okay"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy: phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x7>; + + interrupts-extended = <&tlmm 121 IRQ_TYPE_EDGE_FALLING>; + device_type = "ethernet-phy"; + reset-gpios = <&tlmm 104 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + snps,tx-sched-wrr; + + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + }; +}; + &gcc { clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, @@ -446,6 +499,57 @@ &sdhc_2 { status = "okay"; }; +&tlmm { + ethernet_defaults: ethernet-defaults-state { + mdc-pins { + pins = "gpio113"; + function = "rgmii"; + bias-pull-up; + }; + + mdio-pins { + pins = "gpio114"; + function = "rgmii"; + bias-pull-up; + }; + + rgmii-rx-pins { + pins = "gpio81", "gpio82", "gpio83", "gpio102", "gpio103", "gpio112"; + function = "rgmii"; + bias-disable; + drive-strength = <2>; + }; + + rgmii-tx-pins { + pins = "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97"; + function = "rgmii"; + bias-pull-up; + drive-strength = <16>; + }; + + phy-intr-pins { + pins = "gpio121"; + function = "gpio"; + bias-disable; + drive-strength = <8>; + }; + + pps-pins { + pins = "gpio91"; + function = "rgmii"; + bias-disable; + drive-strength = <8>; + }; + + phy-reset-pins { + pins = "gpio104"; + function = "gpio"; + bias-pull-up; + drive-strength = <16>; + }; + }; +}; + &uart0 { status = "okay"; }; -- 2.34.1 This board expects the MAC to add the delay. Set `phy-mode = "rgmii-id"` in DTS to match upstream definition and work correctly with the updated driver, which switches the semantic handling of 'rgmii' and 'rgmii-id'. Breaking ABI compatibility is acceptable for this board, as it has no known users or interest from any users. Signed-off-by: Yijie Yang --- arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts index 358827c2fbd3..a3e67e83f69f 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts +++ b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts @@ -25,7 +25,7 @@ ðernet { pinctrl-0 = <ðernet_defaults>; phy-handle = <&phy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; mdio { #address-cells = <1>; #size-cells = <0>; -- 2.34.1 This board expects the MAC to add the delay. Set `phy-mode = "rgmii-id"` in DTS to match upstream definition and work correctly with the updated driver, which switches the semantic handling of 'rgmii' and 'rgmii-id'. Breaking ABI compatibility is acceptable for this board, as it has no known users or interest from any users. Signed-off-by: Yijie Yang --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 388d5ecee949..4ac1a5b09e30 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -325,7 +325,7 @@ ðernet { pinctrl-0 = <ðernet_defaults>; phy-handle = <&rgmii_phy>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; mdio { compatible = "snps,dwmac-mdio"; -- 2.34.1