Subject net: stmmac: eic7700: fix delay calculation and initialization ordering
Author lizhi2@eswincomputing.com
Date 2026-05-18 02:20:23 +0000 UTC
Version
Cc alexandre.torgue@foss.st.com andrew@lunn.ch conor.dooley@microchip.com conor@kernel.org davem@davemloft.net devicetree@vger.kernel.org edumazet@google.com krzk@kernel.org kuba@kernel.org linmin@eswincomputing.com linux-arm-kernel@lists.infradead.org linux-kernel@vger.kernel.org linux-stm32@st-md-mailman.stormreply.com lizhi2@eswincomputing.com maxime.chevallier@bootlin.com mcoquelin.stm32@gmail.com netdev@vger.kernel.org ningyu@eswincomputing.com pabeni@redhat.com pinkesh.vaghela@einfochips.com pritesh.patel@einfochips.com rmk@armlinux.org.uk robh@kernel.org weishangjuan@eswincomputing.com
Patches (5)
Name Content [All]
[PATCH net v2 1/5] dt-bindings: ethernet: eswin: add optional TXD and RXD delay register offsets [Body]
[PATCH net v2 2/5] net: stmmac: eswin: fix HSP CSR init ordering after clock enable [Body]
[PATCH net v2 3/5] net: stmmac: eswin: clear TXD and RXD delay registers during initialization [Body]
[PATCH net v2 4/5] net: stmmac: eswin: correct RGMII delay granularity to 20 ps [Body]
[PATCH net v2 5/5] net: stmmac: eswin: validate RGMII delay values [Body]
Series Summary
Passed
✓ All tests passed. No findings.
Sessions
Session 2026-05-18
Passed
ID (for dev) ab26047b-f16d-4a3e-8fdc-869b94f02c81
Status finished
Triaged OK [Log]
Execution Log [Link]
Test Base Patched Verdict
[KASAN] Build Base aaec7096f9961eb223b5b149abe9495525c205d9 [Config] passed [Log]
[KASAN] Boot test: Base aaec7096f9961eb223b5b149abe9495525c205d9 [Config] passed [Log]
[KASAN] Build Patched aaec7096f9961eb223b5b149abe9495525c205d9 [Config] [patched] passed [Log]
[KASAN] Boot test: Patched aaec7096f9961eb223b5b149abe9495525c205d9 [Config] [patched] passed [Log]
[KASAN] Fuzz aaec7096f9961eb223b5b149abe9495525c205d9 [Config] aaec7096f9961eb223b5b149abe9495525c205d9 [Config] [patched] skipped [Log] [Artifacts]