Subject Tegra114: Fix CPU DFLL voltages
Author devnull@kernel.org
Date 2026-10-29 09:32:59 +0000 UTC
Version
Cc admin@tsv-stahl-riesa.de bmasney@redhat.com clamor95@gmail.com devnull@kernel.org jbrunet@baylibre.com jonathanh@nvidia.com linux-clk@vger.kernel.org linux-kernel@vger.kernel.org linux-tegra@vger.kernel.org mperttunen@nvidia.com pgaikwad@nvidia.com sboyd@kernel.org stable@vger.kernel.org thierry.reding@kernel.org
Patches (3)
Name Content [All]
[PATCH 1/3] soc/tegra: fuse: Fix Tegra114 speedo fuse offsets [Body]
[PATCH 2/3] soc/tegra: fuse: Store Tegra114 CPU and SoC speedo values [Body]
[PATCH 3/3] clk: tegra: dfll: Get the voltage step of range-based regulators [Body]
Series Summary
skipped
Session skipped: AI determined the patch has no functional impact
Sessions
Session 2026-10-29
skipped
ID (for dev) f2d4e5e5-7376-4b42-bc43-f130a250b7aa
Status skipped
Triaged Skipped: AI determined the patch has no functional impact [Log] [Trajectory]
Execution Log [Link]
Test Base Patched Verdict