Syzbot CI

Subject	Rework dpll pin control
Author	sergey.temerkhanov@intel.com
Date	2026-08-31 14:50:00 +0000 UTC
Version
Cc	intel-wired-lan@lists.osuosl.org netdev@vger.kernel.org sergey.temerkhanov@intel.com

Patches (6)

Expand

Name	Content [All]
[PATCH iwl-next v5 1/6] ice: dpll: Add the MUX tables to the documentation	[Body]
[PATCH iwl-next v5 2/6] ice: dpll: Rework multiplexed pin notifications	[Body]
[PATCH iwl-next v5 3/6] ice: dpll: Use switch statements to handle pin states	[Body]
[PATCH iwl-next v5 4/6] ice: dpll: Check for bounds when updating the pin states	[Body]
[PATCH iwl-next v5 5/6] ice: dpll: Rework U.FL muxed pin (SMA) control	[Body]
[PATCH iwl-next v5 6/6] ice: dpll: Rework the SMA control logic to match the requirements	[Body]

Series Summary

skipped

Session skipped: AI determined the patch has no functional impact

Sessions

Session 2026-08-31

skipped

ID (for dev)	05531ac1-0107-4756-a79d-4136dca00b72
Status	skipped
Triaged	Skipped: AI determined the patch has no functional impact [Log] [Trajectory]
Execution Log	[Link]

Test	Base	Patched	Verdict