From: Mike Marciniszyn (Meta) This allows for support of 50GR2 and 100GR2 by extending the current singleton mdiodev to an array. DW XPCS can support 25GR1 and 50GR1 using just a single group channel. To operate at 50R2 or 100R2 we need both halves of the channel combined into one group channel device. Adjust current use of singleton mdiodev to use the 0th element. Signed-off-by: Mike Marciniszyn (Meta) Signed-off-by: Alexander Duyck --- drivers/net/pcs/pcs-xpcs-wx.c | 4 ++-- drivers/net/pcs/pcs-xpcs.c | 43 +++++++++++++++++++++-------------------- drivers/net/pcs/pcs-xpcs.h | 5 ++++- 3 files changed, 28 insertions(+), 24 deletions(-) diff --git a/drivers/net/pcs/pcs-xpcs-wx.c b/drivers/net/pcs/pcs-xpcs-wx.c index fc52f7aa5f59..38c980f974b4 100644 --- a/drivers/net/pcs/pcs-xpcs-wx.c +++ b/drivers/net/pcs/pcs-xpcs-wx.c @@ -123,7 +123,7 @@ static int txgbe_pcs_poll_power_up(struct dw_xpcs *xpcs) 10000, 1000000, false, xpcs, DW_VR_XS_PCS_DIG_STS); if (ret < 0) - dev_err(&xpcs->mdiodev->dev, "xpcs power-up timeout\n"); + dev_err(&xpcs->mdiodev[0]->dev, "xpcs power-up timeout\n"); return ret; } @@ -139,7 +139,7 @@ static int txgbe_pma_init_done(struct dw_xpcs *xpcs) 100000, 10000000, false, xpcs, DW_VR_XS_PCS_DIG_CTRL1); if (ret < 0) - dev_err(&xpcs->mdiodev->dev, "xpcs pma initialization timeout\n"); + dev_err(&xpcs->mdiodev[0]->dev, "xpcs pma initialization timeout\n"); return ret; } diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index e69fa2f0a0e8..22246abec948 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -211,23 +211,24 @@ static bool __xpcs_linkmode_supported(const struct dw_xpcs_compat *compat, int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg) { - return mdiodev_c45_read(xpcs->mdiodev, dev, reg); + return mdiodev_c45_read(xpcs->mdiodev[0], dev, reg); } int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val) { - return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val); + return mdiodev_c45_write(xpcs->mdiodev[0], dev, reg, val); } int xpcs_modify(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set) { - return mdiodev_c45_modify(xpcs->mdiodev, dev, reg, mask, set); + return mdiodev_c45_modify(xpcs->mdiodev[0], dev, reg, mask, set); } static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set) { - return mdiodev_c45_modify_changed(xpcs->mdiodev, dev, reg, mask, set); + return mdiodev_c45_modify_changed(xpcs->mdiodev[0], dev, reg, + mask, set); } static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg) @@ -304,7 +305,7 @@ static int xpcs_soft_reset(struct dw_xpcs *xpcs, #define xpcs_warn(__xpcs, __state, __args...) \ ({ \ if ((__state)->link) \ - dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \ + dev_warn(&(__xpcs)->mdiodev[0]->dev, ##__args); \ }) static int xpcs_read_fault_c73(struct dw_xpcs *xpcs, @@ -400,7 +401,7 @@ static void xpcs_link_up_usxgmii(struct dw_xpcs *xpcs, int speed) return; out: - dev_err(&xpcs->mdiodev->dev, "%s: XPCS access returned %pe\n", + dev_err(&xpcs->mdiodev[0]->dev, "%s: XPCS access returned %pe\n", __func__, ERR_PTR(ret)); } @@ -726,7 +727,7 @@ static void xpcs_pre_config(struct phylink_pcs *pcs, phy_interface_t interface) ret = xpcs_switch_interface_mode(xpcs, interface); if (ret) - dev_err(&xpcs->mdiodev->dev, "switch interface failed: %pe\n", + dev_err(&xpcs->mdiodev[0]->dev, "switch interface failed: %pe\n", ERR_PTR(ret)); if (!xpcs->need_reset) @@ -734,14 +735,14 @@ static void xpcs_pre_config(struct phylink_pcs *pcs, phy_interface_t interface) compat = xpcs_find_compat(xpcs, interface); if (!compat) { - dev_err(&xpcs->mdiodev->dev, "unsupported interface %s\n", + dev_err(&xpcs->mdiodev[0]->dev, "unsupported interface %s\n", phy_modes(interface)); return; } ret = xpcs_soft_reset(xpcs, compat); if (ret) - dev_err(&xpcs->mdiodev->dev, "soft reset failed: %pe\n", + dev_err(&xpcs->mdiodev[0]->dev, "soft reset failed: %pe\n", ERR_PTR(ret)); xpcs->need_reset = false; @@ -1189,30 +1190,30 @@ static void xpcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, switch (compat->an_mode) { case DW_10GBASER: - phylink_mii_c45_pcs_get_state(xpcs->mdiodev, state); + phylink_mii_c45_pcs_get_state(xpcs->mdiodev[0], state); break; case DW_AN_C73: ret = xpcs_get_state_c73(xpcs, state, compat); if (ret) - dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", + dev_err(&xpcs->mdiodev[0]->dev, "%s returned %pe\n", "xpcs_get_state_c73", ERR_PTR(ret)); break; case DW_AN_C37_SGMII: ret = xpcs_get_state_c37_sgmii(xpcs, state); if (ret) - dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", + dev_err(&xpcs->mdiodev[0]->dev, "%s returned %pe\n", "xpcs_get_state_c37_sgmii", ERR_PTR(ret)); break; case DW_AN_C37_1000BASEX: ret = xpcs_get_state_c37_1000basex(xpcs, neg_mode, state); if (ret) - dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", + dev_err(&xpcs->mdiodev[0]->dev, "%s returned %pe\n", "xpcs_get_state_c37_1000basex", ERR_PTR(ret)); break; case DW_2500BASEX: ret = xpcs_get_state_2500basex(xpcs, state); if (ret) - dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", + dev_err(&xpcs->mdiodev[0]->dev, "%s returned %pe\n", "xpcs_get_state_2500basex", ERR_PTR(ret)); break; default: @@ -1232,14 +1233,14 @@ static void xpcs_link_up_sgmii_1000basex(struct dw_xpcs *xpcs, if (interface == PHY_INTERFACE_MODE_1000BASEX) { if (speed != SPEED_1000) { - dev_err(&xpcs->mdiodev->dev, + dev_err(&xpcs->mdiodev[0]->dev, "%s: speed %dMbps not supported\n", __func__, speed); return; } if (duplex != DUPLEX_FULL) - dev_err(&xpcs->mdiodev->dev, + dev_err(&xpcs->mdiodev[0]->dev, "%s: half duplex not supported\n", __func__); } @@ -1247,7 +1248,7 @@ static void xpcs_link_up_sgmii_1000basex(struct dw_xpcs *xpcs, ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, mii_bmcr_encode_fixed(speed, duplex)); if (ret) - dev_err(&xpcs->mdiodev->dev, "%s: xpcs_write returned %pe\n", + dev_err(&xpcs->mdiodev[0]->dev, "%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret)); } @@ -1533,7 +1534,7 @@ static struct dw_xpcs *xpcs_create_data(struct mdio_device *mdiodev) return ERR_PTR(-ENOMEM); mdio_device_get(mdiodev); - xpcs->mdiodev = mdiodev; + xpcs->mdiodev[0] = mdiodev; xpcs->pcs.ops = &xpcs_phylink_ops; xpcs->pcs.poll = true; @@ -1542,7 +1543,7 @@ static struct dw_xpcs *xpcs_create_data(struct mdio_device *mdiodev) static void xpcs_free_data(struct dw_xpcs *xpcs) { - mdio_device_put(xpcs->mdiodev); + mdio_device_put(xpcs->mdiodev[0]); kfree(xpcs); } @@ -1552,7 +1553,7 @@ static int xpcs_init_clks(struct dw_xpcs *xpcs) [DW_XPCS_CORE_CLK] = "core", [DW_XPCS_PAD_CLK] = "pad", }; - struct device *dev = &xpcs->mdiodev->dev; + struct device *dev = &xpcs->mdiodev[0]->dev; int ret, i; for (i = 0; i < DW_XPCS_NUM_CLKS; ++i) @@ -1580,7 +1581,7 @@ static int xpcs_init_id(struct dw_xpcs *xpcs) { const struct dw_xpcs_info *info; - info = dev_get_platdata(&xpcs->mdiodev->dev); + info = dev_get_platdata(&xpcs->mdiodev[0]->dev); if (!info) { xpcs->info.pcs = DW_XPCS_ID_NATIVE; xpcs->info.pma = DW_XPCS_PMA_ID_NATIVE; diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h index 929fa238445e..5c804cfd47d3 100644 --- a/drivers/net/pcs/pcs-xpcs.h +++ b/drivers/net/pcs/pcs-xpcs.h @@ -105,10 +105,13 @@ enum dw_xpcs_clock { DW_XPCS_NUM_CLKS, }; +/* 2 channels per group DW PCS devices */ +#define DW_XPCS_MAX_CHANNELS 2 + struct dw_xpcs { struct dw_xpcs_info info; const struct dw_xpcs_desc *desc; - struct mdio_device *mdiodev; + struct mdio_device *mdiodev[DW_XPCS_MAX_CHANNELS]; struct clk_bulk_data clks[DW_XPCS_NUM_CLKS]; struct phylink_pcs pcs; phy_interface_t interface; From: Mike Marciniszyn (Meta) The DW channel 10g-100g IP builds the PCS out of multiple addr mdio addresses. Add xpcs_create_mdiodevs() and xpcs_create_pcs_mdiodevs calls so that a driver using the above part can tell xpcs the addr values in one call. xpcs_create_data(), xpcs_create(), and xpcs_free_data() are extended to accept a variable number of mdio devices. Existing singleton interfaces are re-cast as a having an array pointing to a single mdio device. Signed-off-by: Mike Marciniszyn (Meta) Signed-off-by: Alexander Duyck --- drivers/net/ethernet/meta/fbnic/fbnic_phylink.c | 4 + drivers/net/pcs/pcs-xpcs.c | 106 ++++++++++++++++++----- drivers/net/pcs/pcs-xpcs.h | 1 include/linux/pcs/pcs-xpcs.h | 2 4 files changed, 88 insertions(+), 25 deletions(-) diff --git a/drivers/net/ethernet/meta/fbnic/fbnic_phylink.c b/drivers/net/ethernet/meta/fbnic/fbnic_phylink.c index 09c5225111be..88fc78d55c7a 100644 --- a/drivers/net/ethernet/meta/fbnic/fbnic_phylink.c +++ b/drivers/net/ethernet/meta/fbnic/fbnic_phylink.c @@ -200,9 +200,11 @@ int fbnic_phylink_create(struct net_device *netdev) struct fbnic_dev *fbd = fbn->fbd; struct phylink_pcs *pcs; struct phylink *phylink; + /* See fbnic_mdio.c addr usage */ + int addrs[] = { 0, 1 }; int err; - pcs = xpcs_create_pcs_mdiodev(fbd->mdio_bus, 0); + pcs = xpcs_create_pcs_mdiodevs(fbd->mdio_bus, addrs, ARRAY_SIZE(addrs)); if (IS_ERR(pcs)) { err = PTR_ERR(pcs); dev_err(fbd->dev, "Failed to create PCS device: %d\n", err); diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index 22246abec948..2e236ff1ad85 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -214,9 +214,18 @@ int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg) return mdiodev_c45_read(xpcs->mdiodev[0], dev, reg); } +static int +xpcs_mdev_write_ch(struct dw_xpcs *xpcs, int ch, int dev, u32 reg, u16 val) +{ + if (ch >= xpcs->channels) + return -ENXIO; + + return mdiodev_c45_write(xpcs->mdiodev[ch], dev, reg, val); +} + int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val) { - return mdiodev_c45_write(xpcs->mdiodev[0], dev, reg, val); + return xpcs_mdev_write_ch(xpcs, 0, dev, reg, val); } int xpcs_modify(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set) @@ -1525,16 +1534,21 @@ static int xpcs_identify(struct dw_xpcs *xpcs) return -ENODEV; } -static struct dw_xpcs *xpcs_create_data(struct mdio_device *mdiodev) +static struct dw_xpcs * +xpcs_create_data(struct mdio_device **mdiodev, int channels) { struct dw_xpcs *xpcs; + int i; xpcs = kzalloc_obj(*xpcs); if (!xpcs) return ERR_PTR(-ENOMEM); - mdio_device_get(mdiodev); - xpcs->mdiodev[0] = mdiodev; + xpcs->channels = channels; + for (i = 0; i < channels; i++) { + mdio_device_get(mdiodev[i]); + xpcs->mdiodev[i] = mdiodev[i]; + } xpcs->pcs.ops = &xpcs_phylink_ops; xpcs->pcs.poll = true; @@ -1543,7 +1557,10 @@ static struct dw_xpcs *xpcs_create_data(struct mdio_device *mdiodev) static void xpcs_free_data(struct dw_xpcs *xpcs) { - mdio_device_put(xpcs->mdiodev[0]); + int i; + + for (i = 0; i < xpcs->channels; i++) + mdio_device_put(xpcs->mdiodev[i]); kfree(xpcs); } @@ -1592,12 +1609,12 @@ static int xpcs_init_id(struct dw_xpcs *xpcs) return xpcs_identify(xpcs); } -static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev) +static struct dw_xpcs *xpcs_create(struct mdio_device **mdiodev, int channels) { struct dw_xpcs *xpcs; int ret; - xpcs = xpcs_create_data(mdiodev); + xpcs = xpcs_create_data(mdiodev, channels); if (IS_ERR(xpcs)) return xpcs; @@ -1628,25 +1645,24 @@ static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev) return ERR_PTR(ret); } -/** - * xpcs_create_mdiodev() - create a DW xPCS instance with the MDIO @addr - * @bus: pointer to the MDIO-bus descriptor for the device to be looked at - * @addr: device MDIO-bus ID - * - * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if - * the PCS device couldn't be found on the bus and other negative errno related - * to the data allocation and MDIO-bus communications. - */ -struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr) +static struct dw_xpcs * +xpcs_create_mdiodevs(struct mii_bus *bus, const int *addrs, int channels) { - struct mdio_device *mdiodev; + struct mdio_device *mdiodev[DW_XPCS_MAX_CHANNELS], *rval; struct dw_xpcs *xpcs; + int i; + + if (!addrs || channels <= 0 || channels > DW_XPCS_MAX_CHANNELS) + return ERR_PTR(-EINVAL); - mdiodev = mdio_device_create(bus, addr); - if (IS_ERR(mdiodev)) - return ERR_CAST(mdiodev); + for (i = 0; i < channels; i++) { + rval = mdio_device_create(bus, addrs[i]); + if (IS_ERR(rval)) + goto out_nomem; + mdiodev[i] = rval; + } - xpcs = xpcs_create(mdiodev); + xpcs = xpcs_create(mdiodev, channels); /* xpcs_create() has taken a refcount on the mdiodev if it was * successful. If xpcs_create() fails, this will free the mdio @@ -1654,9 +1670,51 @@ struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr) * anymore, and putting it here will allow mdio_device_put() in * xpcs_destroy() to automatically free the mdio device. */ - mdio_device_put(mdiodev); + for (i = 0; i < channels; i++) + mdio_device_put(mdiodev[i]); return xpcs; +out_nomem: + while (i--) + mdio_device_free(mdiodev[i]); + return ERR_CAST(rval); +} + +/** + * xpcs_create_pcs_mdiodevs() - create a DW xPCS instance with multiple @addrs + * @bus: pointer to the embedded phylink PCS instance + * @addrs: an array of int + * @channels: the number of addrs items or channels + * + * Return: a pointer to the phylink PCS if successful, otherwise -ENODEV if + * the PCS device couldn't be found on the bus and other negative errno related + * to the data allocation and MDIO-bus communications. + */ +struct phylink_pcs * +xpcs_create_pcs_mdiodevs(struct mii_bus *bus, const int *addrs, int channels) +{ + struct dw_xpcs *xpcs; + + xpcs = xpcs_create_mdiodevs(bus, addrs, channels); + if (IS_ERR(xpcs)) + return ERR_CAST(xpcs); + + return &xpcs->pcs; +} +EXPORT_SYMBOL_GPL(xpcs_create_pcs_mdiodevs); + +/** + * xpcs_create_mdiodev() - create a DW xPCS instance with the MDIO @addr + * @bus: pointer to the MDIO-bus descriptor for the device to be looked at + * @addr: device MDIO-bus ID + * + * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if + * the PCS device couldn't be found on the bus and other negative errno related + * to the data allocation and MDIO-bus communications. + */ +struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr) +{ + return xpcs_create_mdiodevs(bus, &addr, 1); } EXPORT_SYMBOL_GPL(xpcs_create_mdiodev); @@ -1694,7 +1752,7 @@ struct dw_xpcs *xpcs_create_fwnode(struct fwnode_handle *fwnode) if (!mdiodev) return ERR_PTR(-EPROBE_DEFER); - xpcs = xpcs_create(mdiodev); + xpcs = xpcs_create(&mdiodev, 1); /* xpcs_create() has taken a refcount on the mdiodev if it was * successful. If xpcs_create() fails, this will free the mdio diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h index 5c804cfd47d3..36f4906e689a 100644 --- a/drivers/net/pcs/pcs-xpcs.h +++ b/drivers/net/pcs/pcs-xpcs.h @@ -114,6 +114,7 @@ struct dw_xpcs { struct mdio_device *mdiodev[DW_XPCS_MAX_CHANNELS]; struct clk_bulk_data clks[DW_XPCS_NUM_CLKS]; struct phylink_pcs pcs; + int channels; phy_interface_t interface; bool need_reset; u8 eee_mult_fact; diff --git a/include/linux/pcs/pcs-xpcs.h b/include/linux/pcs/pcs-xpcs.h index 36073f7b6bb4..d36904ae7cc9 100644 --- a/include/linux/pcs/pcs-xpcs.h +++ b/include/linux/pcs/pcs-xpcs.h @@ -57,6 +57,8 @@ struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr); struct dw_xpcs *xpcs_create_fwnode(struct fwnode_handle *fwnode); void xpcs_destroy(struct dw_xpcs *xpcs); +struct phylink_pcs * +xpcs_create_pcs_mdiodevs(struct mii_bus *bus, const int *addrs, int channels); struct phylink_pcs *xpcs_create_pcs_mdiodev(struct mii_bus *bus, int addr); void xpcs_destroy_pcs(struct phylink_pcs *pcs); From: Mike Marciniszyn (Meta) The DW PCS IP data sheet calls out the need to populate these vendor registers when operating at speeds above 10Gbps. This change enables the correct FEC settings to enable RS-FEC encoding on the link which is the standard used for most links at these higher speeds. Signed-off-by: Mike Marciniszyn (Meta) Signed-off-by: Alexander Duyck --- drivers/net/pcs/pcs-xpcs.c | 67 ++++++++++++++++++++++++++++++++++++++++++++ drivers/net/pcs/pcs-xpcs.h | 6 ++++ include/uapi/linux/mdio.h | 3 ++ 3 files changed, 76 insertions(+) diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index 2e236ff1ad85..c252f8ba6517 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -1412,6 +1412,69 @@ static int xpcs_read_ids(struct dw_xpcs *xpcs) return 0; } +struct pma_pcs_values { + int channels; + u16 rsfec_ctrl; +}; + +static int +xpcs_config_rsfec_pma(struct dw_xpcs *xpcs, const struct pma_pcs_values *v) +{ + /* fbnic's DW IP exposes the RS-FEC PMA at SEP_PMA1, so use it + * directly. Scanning DEVS1 for the correct PMA MMD is left as future + * work for enabling a non-fbnic device on this PCS. + */ + int pma_mmd = MDIO_MMD_SEP_PMA1; + int ret = 0, i; + + for (i = 0; ret >= 0 && i < v->channels; i++) { + ret = xpcs_mdev_write_ch(xpcs, i, pma_mmd, + MDIO_PMA_RSFEC_CTRL, v->rsfec_ctrl); + } + + return ret; +} + +static int xpcs_25gbaser_pma_config(struct dw_xpcs *xpcs) +{ + const struct pma_pcs_values v = { + .rsfec_ctrl = 0, + .channels = 1, + }; + + return xpcs_config_rsfec_pma(xpcs, &v); +} + +static int xpcs_50gbaser_pma_config(struct dw_xpcs *xpcs) +{ + const struct pma_pcs_values v = { + .rsfec_ctrl = DW_VR_RSFEC_CTRL_TC_PAD_ALTER, + .channels = 1, + }; + + return xpcs_config_rsfec_pma(xpcs, &v); +} + +static int xpcs_50gbaser2_pma_config(struct dw_xpcs *xpcs) +{ + const struct pma_pcs_values v = { + .rsfec_ctrl = DW_VR_RSFEC_CTRL_TC_PAD_ALTER, + .channels = 2, + }; + + return xpcs_config_rsfec_pma(xpcs, &v); +} + +static int xpcs_100gbasep_pma_config(struct dw_xpcs *xpcs) +{ + const struct pma_pcs_values v = { + .rsfec_ctrl = MDIO_PMA_RSFEC_CTRL_4LANE_PMD, + .channels = 2, + }; + + return xpcs_config_rsfec_pma(xpcs, &v); +} + static const struct dw_xpcs_compat synopsys_xpcs_compat[] = { { .interface = PHY_INTERFACE_MODE_USXGMII, @@ -1425,6 +1488,7 @@ static const struct dw_xpcs_compat synopsys_xpcs_compat[] = { .interface = PHY_INTERFACE_MODE_25GBASER, .supported = xpcs_25gbaser_features, .an_mode = DW_AN_C73, + .pma_config = xpcs_25gbaser_pma_config, }, { .interface = PHY_INTERFACE_MODE_XLGMII, .supported = xpcs_xlgmii_features, @@ -1433,14 +1497,17 @@ static const struct dw_xpcs_compat synopsys_xpcs_compat[] = { .interface = PHY_INTERFACE_MODE_50GBASER, .supported = xpcs_50gbaser_features, .an_mode = DW_AN_C73, + .pma_config = xpcs_50gbaser_pma_config, }, { .interface = PHY_INTERFACE_MODE_LAUI, .supported = xpcs_50gbaser2_features, .an_mode = DW_AN_C73, + .pma_config = xpcs_50gbaser2_pma_config, }, { .interface = PHY_INTERFACE_MODE_100GBASEP, .supported = xpcs_100gbasep_features, .an_mode = DW_AN_C73, + .pma_config = xpcs_100gbasep_pma_config, }, { .interface = PHY_INTERFACE_MODE_10GBASER, .supported = xpcs_10gbaser_features, diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h index 36f4906e689a..ab47d6dd050c 100644 --- a/drivers/net/pcs/pcs-xpcs.h +++ b/drivers/net/pcs/pcs-xpcs.h @@ -94,6 +94,12 @@ #define DW_VR_MII_DIG_CTRL2_TX_POL_INV BIT(4) #define DW_VR_MII_DIG_CTRL2_RX_POL_INV BIT(0) +/* Clause 133 defines */ +/* RSFEC transcode pad alter + * DW vendor extension in RS-FEC control + */ +#define DW_VR_RSFEC_CTRL_TC_PAD_ALTER BIT(10) + #define DW_XPCS_INFO_DECLARE(_name, _pcs, _pma) \ static const struct dw_xpcs_info _name = { .pcs = _pcs, .pma = _pma } diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h index b2541c948fc1..5219c877b2cf 100644 --- a/include/uapi/linux/mdio.h +++ b/include/uapi/linux/mdio.h @@ -317,6 +317,9 @@ #define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */ #define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */ +/* RSFEC PMA Control register */ +#define MDIO_PMA_RSFEC_CTRL_4LANE_PMD BIT(3) + /* PMA 10GBASE-R Fast Retrain status and control register. */ #define MDIO_PMA_10GBR_FSRT_ENABLE 0x0001 /* Fast retrain enable */ From: Mike Marciniszyn (Meta) This patch introduces the configuration of vendor specific registers for alignment encoding, PCS Mode, and VL_INTVL over the one or two instances as required. The DW PCS IP specification calls out the need to configure both lanes identically when using 2 lane modes such as 50-R2 and 100-R2, so the programming is repeated for each channel. The encoding tables are derived from the IEEE 8023-2022 spec sections 82.2.7 and tables 82-2 and 82-3 for the alignment markers and their insertion. Note that there is a conflict between VRs DW_VR_XS_PCS_DIG_STS and the DW_PCS_IP DW_VR_MII_PCS_PCS_MODE. The bit mask for DW_VR_XS_PCS_DIG_STS/RX_FIFO_ERR fits within the reserved bits for the DW PCS IP DW_VR_MII_PCS_PCS_MODE register so there is no issue. There is also a conflict between DW_VR_MII_PCS_VL_INTVL and DW_VR_MII_AN_INTR_STS but an_mode differs, so again there is no issue. Signed-off-by: Mike Marciniszyn (Meta) Signed-off-by: Alexander Duyck --- drivers/net/pcs/pcs-xpcs.c | 96 ++++++++++++++++++++++++++++++++++++++++++++ drivers/net/pcs/pcs-xpcs.h | 25 +++++++++++ 2 files changed, 120 insertions(+), 1 deletion(-) diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index c252f8ba6517..d9c444528f55 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -1412,11 +1412,67 @@ static int xpcs_read_ids(struct dw_xpcs *xpcs) return 0; } +/* m0 - m2 from Table 82-2/82-3 + * m4 - m6 are skipped since they are inversions of m0 - m2. + * Inverted parity fields (IEEE 82.2.8) bip3 and bip7 are omitted. + */ +struct lane_markers { + u8 m0, m1, m2; +}; + +/* Alignment marker encodings, see table 82-2 in IEEE 802.3-2022 */ +static const struct lane_markers xpcs_100gbaser_markers[] = { + {0xc1, 0x68, 0x21}, + {0x9d, 0x71, 0x8e}, + {0x59, 0x4b, 0xe8}, + {0x4d, 0x95, 0x7b}, +}; + +/* Alignment marker encodings, see table 82-3 in IEEE 802.3-2022 + * The content of the 50G markers is identical to 40G values (IEEE 133.2.2). + */ +static const struct lane_markers xpcs_50gbaser_markers[] = { + {0x90, 0x76, 0x47}, + {0xf0, 0xc4, 0xe6}, + {0xc5, 0x65, 0x9b}, + {0xa2, 0x79, 0x3d}, +}; + struct pma_pcs_values { + const struct lane_markers *vl0_markers; + const struct lane_markers *vl123_markers; int channels; u16 rsfec_ctrl; + u16 pcs_mode; + u16 vl_intvl; }; +#define XPCS_VL_TO_REG(vl, lh) \ + (((vl) * 2) + DW_VR_MII_PCS_VL0_##lh) + +static int +xpcs_write_pcs_ch(struct dw_xpcs *xpcs, int ch, int reg, u16 val) +{ + return xpcs_mdev_write_ch(xpcs, ch, MDIO_MMD_PCS, reg, val); +} + +static int xpcs_config_ch_vl_markers(struct dw_xpcs *xpcs, int ch, int vl, + const struct lane_markers *m) +{ + int ret; + + /* m0, m1, m2 written to _L and _H registers + * + * _L = (m1 << 8) | m0 + * _H = m2 + */ + ret = xpcs_write_pcs_ch(xpcs, ch, XPCS_VL_TO_REG(vl, L), + ((u16)m->m1 << 8) | m->m0); + if (ret < 0) + return ret; + return xpcs_write_pcs_ch(xpcs, ch, XPCS_VL_TO_REG(vl, H), m->m2); +} + static int xpcs_config_rsfec_pma(struct dw_xpcs *xpcs, const struct pma_pcs_values *v) { @@ -1425,9 +1481,28 @@ xpcs_config_rsfec_pma(struct dw_xpcs *xpcs, const struct pma_pcs_values *v) * work for enabling a non-fbnic device on this PCS. */ int pma_mmd = MDIO_MMD_SEP_PMA1; - int ret = 0, i; + int ret = 0, i, vl; for (i = 0; ret >= 0 && i < v->channels; i++) { + /* code word markings */ + for (vl = 0; ret >= 0 && vl < 4; vl++) { + const struct lane_markers *m; + + m = vl ? v->vl123_markers + vl - 1 : v->vl0_markers; + ret = xpcs_config_ch_vl_markers(xpcs, i, vl, m); + } + if (ret < 0) + break; + /* vendor registers */ + ret = xpcs_write_pcs_ch(xpcs, i, + DW_VR_MII_PCS_VL_INTVL, v->vl_intvl); + if (ret < 0) + break; + ret = xpcs_write_pcs_ch(xpcs, i, + DW_VR_MII_PCS_PCS_MODE, v->pcs_mode); + if (ret < 0) + break; + /* rsfec register */ ret = xpcs_mdev_write_ch(xpcs, i, pma_mmd, MDIO_PMA_RSFEC_CTRL, v->rsfec_ctrl); } @@ -1440,6 +1515,13 @@ static int xpcs_25gbaser_pma_config(struct dw_xpcs *xpcs) const struct pma_pcs_values v = { .rsfec_ctrl = 0, .channels = 1, + /* 25g markers from 100g and 50g tables per 802.3-2022 + * 108.5.2.4 + */ + .vl0_markers = &xpcs_100gbaser_markers[0], + .vl123_markers = &xpcs_50gbaser_markers[1], + .vl_intvl = 20479, + .pcs_mode = DW_VR_MII_PCS_MODE_CLAUSE107, }; return xpcs_config_rsfec_pma(xpcs, &v); @@ -1450,6 +1532,10 @@ static int xpcs_50gbaser_pma_config(struct dw_xpcs *xpcs) const struct pma_pcs_values v = { .rsfec_ctrl = DW_VR_RSFEC_CTRL_TC_PAD_ALTER, .channels = 1, + .vl0_markers = &xpcs_50gbaser_markers[0], + .vl123_markers = &xpcs_50gbaser_markers[1], + .pcs_mode = 0, + .vl_intvl = 20479, }; return xpcs_config_rsfec_pma(xpcs, &v); @@ -1460,6 +1546,10 @@ static int xpcs_50gbaser2_pma_config(struct dw_xpcs *xpcs) const struct pma_pcs_values v = { .rsfec_ctrl = DW_VR_RSFEC_CTRL_TC_PAD_ALTER, .channels = 2, + .vl0_markers = &xpcs_50gbaser_markers[0], + .vl123_markers = &xpcs_50gbaser_markers[1], + .pcs_mode = 0, + .vl_intvl = 20479, }; return xpcs_config_rsfec_pma(xpcs, &v); @@ -1470,6 +1560,10 @@ static int xpcs_100gbasep_pma_config(struct dw_xpcs *xpcs) const struct pma_pcs_values v = { .rsfec_ctrl = MDIO_PMA_RSFEC_CTRL_4LANE_PMD, .channels = 2, + .vl0_markers = &xpcs_100gbaser_markers[0], + .vl123_markers = &xpcs_100gbaser_markers[1], + .pcs_mode = DW_VR_MII_PCS_MODE_DISABLE_MLD, + .vl_intvl = 16383, }; return xpcs_config_rsfec_pma(xpcs, &v); diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h index ab47d6dd050c..adb7b1c13c2d 100644 --- a/drivers/net/pcs/pcs-xpcs.h +++ b/drivers/net/pcs/pcs-xpcs.h @@ -100,6 +100,31 @@ */ #define DW_VR_RSFEC_CTRL_TC_PAD_ALTER BIT(10) +/* Vendor specific 4 channel PCS registers */ + +/* DW_VR_MII_PCS_VL_INTVL and DW_VR_MII_AN_INTR_STS conflict + * but code paths are different + */ +#define DW_VR_MII_PCS_VL_INTVL 0x8002 +/* 0x8008 - 0x800f */ +#define DW_VR_MII_PCS_VL0_L 0x8008 +#define DW_VR_MII_PCS_VL0_H 0x8009 +#define DW_VR_MII_PCS_PCS_MODE 0x8010 + +/* DW_VR_MII_PCS_PCS_MODE bits */ +#define DW_VR_MII_PCS_MODE_HI_BER25 BIT(2) +#define DW_VR_MII_PCS_MODE_DISABLE_MLD BIT(1) +#define DW_VR_MII_PCS_MODE_CLAUSE49 BIT(0) + +/* 25G requires these two bits are set. + * + * The CLAUSE49 bit changes the interface with the MAC + * to 64 bit and the BER25 bit changes the measurement + * interval to 2ms. + */ +#define DW_VR_MII_PCS_MODE_CLAUSE107 \ + (DW_VR_MII_PCS_MODE_HI_BER25 | DW_VR_MII_PCS_MODE_CLAUSE49) + #define DW_XPCS_INFO_DECLARE(_name, _pcs, _pma) \ static const struct dw_xpcs_info _name = { .pcs = _pcs, .pma = _pma }