Implement CPUID leaf 0x80000026 (AMD Extended CPU Topology). It presents the complete topology information to guests via a single CPUID with multiple subleafs, each describing a specific hierarchy level, viz. core, complex, die, socket. Note that complex/CCX level relates to "die" in QEMU, and die/CCD level is not supported in QEMU yet. Hence, use CCX at CCD level until diegroups are implemented. Signed-off-by: Shivansh Dhiman --- target/i386/cpu.c | 76 +++++++++++++++++++++++++++++++++++++++++++ target/i386/kvm/kvm.c | 17 ++++++++++ 2 files changed, 93 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 641777578637..b7827e448aa5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -495,6 +495,78 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, assert(!(*eax & ~0x1f)); } +/* + * CPUID_Fn80000026: Extended CPU Topology + * + * EAX Bits Description + * 31:5 Reserved + * 4:0 Number of bits to shift Extended APIC ID right to get a unique + * topology ID of the current hierarchy level. + * + * EBX Bits Description + * 31:16 Reserved + * 15:0 Number of logical processors at the current hierarchy level. + * + * ECX Bits Description + * 31:16 Reserved + * 15:8 Level Type. Values: + * Value Description + * 0h Reserved + * 1h Core + * 2h Complex + * 3h Die + * 4h Socket + * FFh-05h Reserved + * 7:0 Input ECX + * + * EDX Bits Description + * 31:0 Extended APIC ID of the logical processor + */ +static void encode_topo_cpuid80000026(CPUX86State *env, uint32_t count, + X86CPUTopoInfo *topo_info, + uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx) +{ + X86CPU *cpu = env_archcpu(env); + uint32_t shift, nr_logproc, lvl_type; + + switch (count) { + case 0: + shift = apicid_core_offset(topo_info); + nr_logproc = num_threads_by_topo_level(topo_info, CPU_TOPOLOGY_LEVEL_CORE); + lvl_type = 1; + break; + + case 1: + shift = apicid_die_offset(topo_info); + nr_logproc = num_threads_by_topo_level(topo_info, CPU_TOPOLOGY_LEVEL_DIE); + lvl_type = 2; + break; + + case 2: + shift = apicid_die_offset(topo_info); + nr_logproc = num_threads_by_topo_level(topo_info, CPU_TOPOLOGY_LEVEL_DIE); + lvl_type = 3; + break; + + case 3: + shift = apicid_pkg_offset(topo_info); + nr_logproc = num_threads_by_topo_level(topo_info, CPU_TOPOLOGY_LEVEL_SOCKET); + lvl_type = 4; + break; + + default: + shift = 0; + nr_logproc = 0; + lvl_type = 0; + } + + *eax = shift & 0x1F; + *ebx = nr_logproc; + *ecx = ((lvl_type & 0xFF) << 8) | (count & 0xFF); + *edx = cpu->apic_id; +} + /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) { @@ -8554,6 +8626,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, R_EBX) & 0xf; } break; + case 0x80000026: + /* AMD Extended CPU Topology */ + encode_topo_cpuid80000026(env, count, topo_info, eax, ebx, ecx, edx); + break; case 0xC0000000: *eax = env->cpuid_xlevel2; *ebx = 0; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 60c798113823..ed3d40bf073e 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2037,6 +2037,23 @@ uint32_t kvm_x86_build_cpuid(CPUX86State *env, struct kvm_cpuid_entry2 *entries, c = &entries[cpuid_i++]; } break; + case 0x80000026: + /* Query for all AMD extended topology information leaves */ + for (j = 0; ; j++) { + c->function = i; + c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; + c->index = j; + cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); + + if (((c->ecx >> 8) & 0xFF) == 0) { + break; + } + if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { + goto full; + } + c = &entries[cpuid_i++]; + } + break; default: c->function = i; c->flags = 0; -- 2.43.0 Introduce new CPU property x-force-cpuid-0x80000026 using which the CPUID 0x80000026 is enabled. It defaults to false. If a vCPU's model is host, then CPUID is enabled based on CPU family/model. Implement x86_is_amd_zen4_or_above() helper to detect Zen4+ CPUs using family/model. Signed-off-by: Shivansh Dhiman --- target/i386/cpu.c | 8 ++++++++ target/i386/cpu.h | 18 ++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b7827e448aa5..01c4da7cf134 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9158,6 +9158,12 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); } + + /* Enable CPUID[0x80000026] for AMD Genoa models and above */ + if (cpu->force_cpuid_0x80000026 || + (!xcc->model && x86_is_amd_zen4_or_above(cpu))) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000026); + } } /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ @@ -10133,6 +10139,8 @@ static const Property x86_cpu_properties[] = { arch_cap_always_on, false), DEFINE_PROP_BOOL("x-pdcm-on-even-without-pmu", X86CPU, pdcm_on_even_without_pmu, false), + DEFINE_PROP_BOOL("x-force-cpuid-0x80000026", X86CPU, force_cpuid_0x80000026, + false), }; #ifndef CONFIG_USER_ONLY diff --git a/target/i386/cpu.h b/target/i386/cpu.h index cee1f692a1c3..0fecca26dc4a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2292,6 +2292,9 @@ struct ArchCPU { /* Force to enable cpuid 0x1f */ bool force_cpuid_0x1f; + /* Force to enable cpuid 0x80000026 */ + bool force_cpuid_0x80000026; + /* Enable auto level-increase for all CPUID leaves */ bool full_cpuid_auto_level; @@ -2879,6 +2882,21 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen); uint32_t xsave_area_size(uint64_t mask, bool compacted); void x86_update_hflags(CPUX86State* env); +static inline bool x86_is_amd_zen4_or_above(X86CPU *cpu) +{ + uint32_t family = x86_cpu_family(cpu->env.cpuid_version); + uint32_t model = x86_cpu_model(cpu->env.cpuid_version); + + if (!IS_AMD_CPU(&cpu->env) || family < 0x19) { + return false; + } + if (family > 0x19) { + return true; + } + return (model >= 0x10 && model <= 0x1f) || + (model >= 0x60 && model <= 0xaf); +} + static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat) { return !!(cpu->hyperv_features & BIT(feat)); -- 2.43.0 Enable CPUID leaf 0x80000026 (Extended CPU Topology) for AMD Zen4+ processors, i.e, Genoa and above. Add version 3 to EPYC-Genoa and version 2 to EPYC-Turin CPU models with x-force-cpuid-0x80000026 property enabled. Signed-off-by: Shivansh Dhiman --- target/i386/cpu.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 01c4da7cf134..12500d6b7bed 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6505,6 +6505,13 @@ static const X86CPUDefinition builtin_x86_defs[] = { }, .cache_info = &epyc_genoa_v2_cache_info }, + { + .version = 3, + .props = (PropValue[]) { + { "x-force-cpuid-0x80000026", "on" }, + { /* end of list */ } + } + }, { /* end of list */ } } }, @@ -6735,6 +6742,17 @@ static const X86CPUDefinition builtin_x86_defs[] = { .xlevel = 0x80000022, .model_id = "AMD EPYC-Turin Processor", .cache_info = &epyc_turin_cache_info, + .versions = (X86CPUVersionDefinition[]) { + { .version = 1 }, + { + .version = 2, + .props = (PropValue[]) { + { "x-force-cpuid-0x80000026", "on" }, + { /* end of list */ } + } + }, + { /* end of list */ } + } }, }; -- 2.43.0 From: Ravi Bangoria Bus Lock Detect is enumerated with cpuid Fn0000_0007_ECX_x0 bit [24 / BUSLOCKTRAP]. It can be enabled through MSR_IA32_DEBUGCTLMSR. When enabled, hardware clears DR6[11] and raises a #DB exception on occurrence of Bus Lock if CPL > 0. More detail about the feature can be found in AMD APM[1]. Qemu supports remote debugging through host gdb (the "gdbstub" facility) where some of the remote debugging features like instruction and data breakpoints relies on the same hardware infrastructure (#DB, DR6 etc.) that Bus Lock Detect also uses. Instead of handling internally, KVM forwards #DB to Qemu when remote debugging is ON and #DB is being intercepted. It's Qemu's responsibility to re-inject the exception to guest when some of the exception source bits (in DR6) are not being handled by Qemu remote debug handler. Bus Lock Detect is one such case. [1]: AMD64 Architecture Programmer's Manual Pub. 40332, Rev. 4.07 - June 2023, Vol 2, 13.1.3.6 Bus Lock Trap https://bugzilla.kernel.org/attachment.cgi?id=304653 Signed-off-by: Ravi Bangoria Signed-off-by: Shivansh Dhiman --- target/i386/cpu.h | 1 + target/i386/kvm/kvm.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0fecca26dc4a..852b3a33b54d 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -276,6 +276,7 @@ typedef enum X86Seg { | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK \ | CR4_LAM_SUP_MASK | CR4_FRED_MASK)) +#define DR6_BLD (1 << 11) #define DR6_BD (1 << 13) #define DR6_BS (1 << 14) #define DR6_BT (1 << 15) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index ed3d40bf073e..00c44c2de650 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -5864,14 +5864,14 @@ static int kvm_handle_debug(X86CPU *cpu, } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) { ret = EXCP_DEBUG; } - if (ret == 0) { + if (ret == 0 || !(arch_info->dr6 & DR6_BLD)) { cpu_synchronize_state(cs); assert(env->exception_nr == -1); /* pass to guest */ kvm_queue_exception(env, arch_info->exception, arch_info->exception == EXCP01_DB, - arch_info->dr6); + ret == 0 ? arch_info->dr6 ^ DR6_BLD : DR6_BLD); env->has_error_code = 0; } -- 2.43.0 Enable the Bus Lock Detect feature for the EPYC-Turin-v2 CPU model to match the hardware capabilities of AMD Turin processors. This feature allows detection of split locks and bus locks, which can cause performance degradation in multi-core systems. The bus-lock-detect feature is part of the architectural capabilities exposed through CPUID and should be enabled by default for Turin v2 and later CPU models. Signed-off-by: Shivansh Dhiman --- target/i386/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 12500d6b7bed..660b9c2a98b6 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6748,6 +6748,7 @@ static const X86CPUDefinition builtin_x86_defs[] = { .version = 2, .props = (PropValue[]) { { "x-force-cpuid-0x80000026", "on" }, + { "bus-lock-detect", "on" }, { /* end of list */ } } }, -- 2.43.0