From: Wu Fei Introduce the user-space API data for RISC-V IOMMU nested domains: - IOMMU_HWPT_DATA_RISCV_S1 together with struct iommu_hwpt_riscv, which carries the first-stage(guest) device-context fields (tc and iosatp) for allocating a nested hwpt; - IOMMU_VIOMMU_TYPE_RISCV so user space can request a RISC-V IOMMU vIOMMU object. Signed-off-by: Wu Fei Co-developed-by: Gong Shuai Signed-off-by: Gong Shuai --- include/uapi/linux/iommufd.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 206fa667c782..7458878386c5 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -506,18 +506,31 @@ struct iommu_hwpt_amd_guest { __aligned_u64 dte[4]; }; +/** + * struct iommu_hwpt_riscv - RISC-V IOMMU stage-1 page table data + * (IOMMU_HWPT_DATA_RISCV_S1) + * @tc: Guest device context translation control + * @iosatp: Guest device context stage-1 root page table pointer + */ +struct iommu_hwpt_riscv { + __aligned_u64 tc; + __aligned_u64 iosatp; +}; + /** * enum iommu_hwpt_data_type - IOMMU HWPT Data Type * @IOMMU_HWPT_DATA_NONE: no data * @IOMMU_HWPT_DATA_VTD_S1: Intel VT-d stage-1 page table * @IOMMU_HWPT_DATA_ARM_SMMUV3: ARM SMMUv3 Context Descriptor Table * @IOMMU_HWPT_DATA_AMD_GUEST: AMD IOMMU guest page table + * @IOMMU_HWPT_DATA_RISCV_S1: RISC-V IOMMU stage-1 page table */ enum iommu_hwpt_data_type { IOMMU_HWPT_DATA_NONE = 0, IOMMU_HWPT_DATA_VTD_S1 = 1, IOMMU_HWPT_DATA_ARM_SMMUV3 = 2, IOMMU_HWPT_DATA_AMD_GUEST = 3, + IOMMU_HWPT_DATA_RISCV_S1 = 4, }; /** @@ -1095,6 +1108,7 @@ struct iommu_fault_alloc { * @IOMMU_VIOMMU_TYPE_ARM_SMMUV3: ARM SMMUv3 driver specific type * @IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for ARM * SMMUv3) enabled ARM SMMUv3 type + * @IOMMU_VIOMMU_TYPE_RISCV: RISC-V IOMMU driver specific type */ enum iommu_viommu_type { IOMMU_VIOMMU_TYPE_DEFAULT = 0, @@ -1105,6 +1119,7 @@ enum iommu_viommu_type { * VMM must wire the HYP_OWN bit to 0 in guest VINTF_CONFIG register */ IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV = 2, + IOMMU_VIOMMU_TYPE_RISCV = 3, }; /** -- 2.53.0