A hart may describe its atomics as "a", or as "zaamo" and "zalrsc". The two are the same thing: the A extension is defined as Zaamo plus Zalrsc. The kernel already expands "a" into both sub-extensions, but not the other way round, so a hart that lists the sub-extensions ends up without RISCV_ISA_EXT_A. /proc/cpuinfo then shows rv64imfdc... and the A bit is missing from ELF hwcap, although the hardware is the same as one that lists "a". Set A in the source ISA bitmap when both Zaamo and Zalrsc are there, before the bitmap is resolved, so that hwcap and cpuinfo do not depend on how the firmware spelled it. This covers the "riscv,isa" string and ACPI as well as "riscv,isa-extensions". Signed-off-by: Vladimir Kondratiev --- arch/riscv/kernel/cpufeature.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 7329792978cc..45684e129be1 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -682,6 +682,15 @@ static void __init riscv_resolve_isa(unsigned long *source_isa, int max_loop_count = riscv_isa_ext_count, ret; unsigned int bit; + /* + * "a" is exactly Zaamo plus Zalrsc. A hart that lists both has A, + * however the firmware spelled it, so report it the same way in + * ELF hwcap and /proc/cpuinfo. + */ + if (test_bit(RISCV_ISA_EXT_ZAAMO, source_isa) && + test_bit(RISCV_ISA_EXT_ZALRSC, source_isa)) + set_bit(RISCV_ISA_EXT_A, source_isa); + do { loop = false; if (max_loop_count-- < 0) { -- 2.43.0