From: Charlie-cy Wu mt7925_load_clc() is shared by MT7925, MT7927 and MT7928 (0x7935 is folded into 0x7928 in pci.c). The hw type sanity check it does on every CLC region is MT7925-specific twice over: the encap bits live at efuse offset MT_EE_HW_TYPE (0xa71) in the MT7925 layout, and only MT7925 CLC blobs carry that hw type in their t0/t2 header. On MT7927/MT7928 the driver therefore reads a byte that means nothing on those parts and compares it against a header field that was never populated, so a mismatch silently skips every CLC region and leaves phy->clc[] empty - no country/regd table gets installed at all. Gate both the efuse read and the two header checks on is_mt7925(), so MT7927/MT7928 accept the CLC regions from their own firmware as-is. No functional change for MT7925: PCIe still reads 0xa71 and filters by encap type, USB still runs with hw_encap = 0 as before. Fixes: 356b39285559 ("wifi: mt76: connac3: refactor CLC header type validation logic") Signed-off-by: Charlie-cy Wu --- .../net/wireless/mediatek/mt76/mt7925/mcu.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c index bd63789ab8f7..bf2cb6172cc8 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c +++ b/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c @@ -855,7 +855,7 @@ static int mt7925_load_clc(struct mt792x_dev *dev, const char *fw_name) if (!mt7925_regd_clc_supported(dev)) return 0; - if (mt76_is_mmio(&dev->mt76)) { + if (is_mt7925(&dev->mt76) && mt76_is_mmio(&dev->mt76)) { ret = mt7925_mcu_read_eeprom(dev, MT_EE_HW_TYPE, &hw_encap); if (ret) return ret; @@ -906,14 +906,16 @@ static int mt7925_load_clc(struct mt792x_dev *dev, const char *fw_name) if (phy->clc[clc->idx]) continue; - /* header content sanity */ - if ((clc->idx == MT792x_CLC_BE_CTRL || clc->idx == MT792x_CLC_REGD) && - u8_get_bits(clc->t2.type, MT_EE_HW_TYPE_ENCAP) != hw_encap) - continue; + /* header content sanity, only MT7925 encodes hw type in CLC */ + if (is_mt7925(&dev->mt76)) { + if ((clc->idx == MT792x_CLC_BE_CTRL || clc->idx == MT792x_CLC_REGD) && + u8_get_bits(clc->t2.type, MT_EE_HW_TYPE_ENCAP) != hw_encap) + continue; - if (clc->idx != MT792x_CLC_BE_CTRL && clc->idx != MT792x_CLC_REGD && - u8_get_bits(clc->t0.type, MT_EE_HW_TYPE_ENCAP) != hw_encap) - continue; + if (clc->idx != MT792x_CLC_BE_CTRL && clc->idx != MT792x_CLC_REGD && + u8_get_bits(clc->t0.type, MT_EE_HW_TYPE_ENCAP) != hw_encap) + continue; + } phy->clc[clc->idx] = devm_kmemdup(mdev->dev, clc, le32_to_cpu(clc->len), -- 2.18.0