Forcing RGMII mode on extension interface 1 within family D silicon demands an alternative muxing and clock delay path. The driver needs to explicitly reset the hardware TX clock delay line (EXT1_RGMII_TX_DLY) and evaluate the top-level configuration register mux. If the internal MAC4 block is not occupying extension 1, the RGMII/MII pin mux matrix must be bound to MAC7, disabling the conflicting SerDes 1 lane in the process. Signed-off-by: Mieczyslaw Nalewaj --- drivers/net/dsa/realtek/rtl8365mb_main.c | 42 ++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c index 910e868..c638c20 100644 --- a/drivers/net/dsa/realtek/rtl8365mb_main.c +++ b/drivers/net/dsa/realtek/rtl8365mb_main.c @@ -334,6 +334,12 @@ #define RTL8365MB_SDS_OPTION_ARM_KEY 0x0249 #define RTL8365MB_SDS_OPTION_REG 0x13C1 +#define RTL8365MB_D_SDS_MISC_MODE_FIELD_MASK GENMASK(4, 0) +/* Shared "disable" encoding for both SDS_MISC's and SDS1_MISC0's + * 5-bit mode fields. + */ +#define RTL8365MB_D_PORT_SDS_MODE_DISABLE 0x1f + /* Embedded DW8051 microcontroller control registers. The microcontroller * can run firmware to manage the SerDes link, but this driver keeps it in * reset and disabled: phylink already performs the link management that @@ -459,6 +465,15 @@ #define RTL8365MB_PORT_MISC_CFG_VLAN_EGRESS_MODE_MASK GENMASK(5, 4) #define RTL8365MB_PORT_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK GENMASK(3, 0) +#define RTL8365MB_D_REG_EXT_TXC_DLY 0x13f9 +#define RTL8365MB_D_EXT1_RGMII_TX_DLY_MASK GENMASK(5, 3) + +#define RTL8365MB_D_REG_TOP_CON0 0x1d70 +#define RTL8365MB_D_MAC7_SEL_EXT1_MASK BIT(13) +#define RTL8365MB_D_MAC4_SEL_EXT1_MASK BIT(12) + +#define RTL8365MB_D_REG_SDS1_MISC0 0x1d78 + /** * enum rtl8365mb_vlan_egress_mode - port VLAN egress mode * @RTL8365MB_VLAN_EGRESS_MODE_ORIGINAL: follow untag mask in VLAN4k table entry @@ -1208,6 +1223,7 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, struct dsa_port *dp; int tx_delay = 0; int rx_delay = 0; + u32 data; u32 val; int ret; @@ -1277,6 +1293,32 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, if (ret) return ret; + if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D && extint->id == 1) { + ret = regmap_update_bits(priv->map, + RTL8365MB_D_REG_EXT_TXC_DLY, + RTL8365MB_D_EXT1_RGMII_TX_DLY_MASK, 0); + if (ret) + return ret; + /* Configure RGMII/MII mux to port 7 if UTP_PORT4 is not RGMII mode */ + ret = regmap_read(priv->map, RTL8365MB_D_REG_TOP_CON0, &data); + if (ret) + return ret; + if ((data & RTL8365MB_D_MAC4_SEL_EXT1_MASK) == 0) { + ret = regmap_update_bits(priv->map, + RTL8365MB_D_REG_TOP_CON0, + RTL8365MB_D_MAC7_SEL_EXT1_MASK, + RTL8365MB_D_MAC7_SEL_EXT1_MASK); + if (ret) + return ret; + } + ret = regmap_update_bits(priv->map, + RTL8365MB_D_REG_SDS1_MISC0, + RTL8365MB_D_SDS_MISC_MODE_FIELD_MASK, + RTL8365MB_D_PORT_SDS_MODE_DISABLE); + if (ret) + return ret; + } + return 0; } -- 2.53.0