From: Arkadiusz Kubalewski Replace the per-type frequency tables (ice_cgu_pin_freq_1_hz and ice_cgu_pin_freq_10_mhz) and the two-entry ice_cgu_pin_freq_common array with a named range constant ICE_CGU_MAX_FREQ_HZ (25 MHz), a new ice_cgu_pin_freq_range array containing DPLL_PIN_FREQUENCY_RANGE(1, ICE_CGU_MAX_FREQ_HZ), and a separate ice_cgu_pin_freq_gnss array that retains DPLL_PIN_FREQUENCY_1PPS for GNSS input pins. The hardware firmware spec defines an any_freq capability for CGU inputs (ICE_AQC_GET_CGU_IN_CFG_FLG1_ANYFREQ), but the static pin descriptor tables constrained configurable pins to 1PPS or 10MHz, preventing users from setting valid intermediate frequencies. Use a range entry so the DPLL netlink interface correctly reflects what the firmware will accept. The firmware validates the actual value and rejects out-of-range requests. MUX, SyncE ETH port, and configurable EXT pins now advertise the full frequency range, matching the hardware capability. GNSS input pins retain the 1PPS-only advertisement since a GNSS receiver is physically constrained to 1 Hz. Fixes: 6db5f2cd9ebb ("ice: dpll: fix output pin capabilities") Signed-off-by: Arkadiusz Kubalewski Signed-off-by: Aleksandr Loktionov --- drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 128 +++++++++++--------- 1 file changed, 72 insertions(+), 56 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 7b1b402..3949138 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -7,127 +7,143 @@ #include "ice_ptp_hw.h" #include "ice_ptp_consts.h" -static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = { - DPLL_PIN_FREQUENCY_1PPS, - DPLL_PIN_FREQUENCY_10MHZ, -}; +/* Maximum frequency supported by CGU pins, in Hz */ +#define ICE_CGU_MAX_FREQ_HZ 25000000 -static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = { - DPLL_PIN_FREQUENCY_1PPS, +static struct dpll_pin_frequency ice_cgu_pin_freq_range[] = { + DPLL_PIN_FREQUENCY_RANGE(1, ICE_CGU_MAX_FREQ_HZ), }; -static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz[] = { - DPLL_PIN_FREQUENCY_10MHZ, +static struct dpll_pin_frequency ice_cgu_pin_freq_gnss[] = { + DPLL_PIN_FREQUENCY_1PPS, }; static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = { { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, - { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, }, - { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, + { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, + { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, - ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, + ARRAY_SIZE(ice_cgu_pin_freq_gnss), ice_cgu_pin_freq_gnss }, }; static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = { { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, - { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, }, - { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, }, - { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, }, - { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, + { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, + { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, + { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, + { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, - ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, + ARRAY_SIZE(ice_cgu_pin_freq_gnss), ice_cgu_pin_freq_gnss }, }; static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = { { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, - { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, - { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, + { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, + { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, }; static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = { { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, - { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, - { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, - { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, + { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, + { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, + { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, }; static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = { { "NONE", SI_REF0P, 0, 0 }, { "NONE", SI_REF0N, 0, 0 }, - { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX, 0 }, - { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX, 0 }, + { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, + { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "EXT_CLK_SYNC", SI_REF2P, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "NONE", SI_REF2N, 0, 0 }, { "EXT_PPS_OUT", SI_REF3, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "INT_PPS_OUT", SI_REF4, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, }; static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = { { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, - { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, + { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, }; static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = { { "NONE", ZL_REF0P, 0, 0 }, { "INT_PPS_OUT", ZL_REF0N, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, - { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0 }, - { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0 }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, + { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, + { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "NONE", ZL_REF2P, 0, 0 }, { "NONE", ZL_REF2N, 0, 0 }, { "EXT_CLK_SYNC", ZL_REF3P, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "NONE", ZL_REF3N, 0, 0 }, { "EXT_PPS_OUT", ZL_REF4P, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0 }, }; static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = { { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, - { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, - { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, + { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, + { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT, - ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, + ARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range }, { "NONE", ZL_OUT5, 0, 0 }, }; -- 2.52.0