Add driver for the StarFive JHB100 Peripheral-3 clock controller. Signed-off-by: Changhuang Liang --- drivers/clk/starfive/Kconfig | 8 + drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jhb100-per3.c | 189 ++++++++++++++++++ 3 files changed, 198 insertions(+) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per3.c diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index 01d6d325dcd0..c612f1ede7d7 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -97,6 +97,14 @@ config CLK_STARFIVE_JHB100_PER2 Say yes here to support the peripheral-2 clock controller on the StarFive JHB100 SoC. +config CLK_STARFIVE_JHB100_PER3 + bool "StarFive JHB100 peripheral-3 clock support" + depends on CLK_STARFIVE_JHB100_SYS1 + default ARCH_STARFIVE + help + Say yes here to support the peripheral-3 clock controller + on the StarFive JHB100 SoC. + config CLK_STARFIVE_JHB100_SYS0 bool "StarFive JHB100 system-0 clock support" depends on ARCH_STARFIVE || COMPILE_TEST diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index 044e1942ccfa..f00690f0cdad 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) += clk-starfive-jhb100-per0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) += clk-starfive-jhb100-per1.o obj-$(CONFIG_CLK_STARFIVE_JHB100_PER2) += clk-starfive-jhb100-per2.o +obj-$(CONFIG_CLK_STARFIVE_JHB100_PER3) += clk-starfive-jhb100-per3.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per3.c b/drivers/clk/starfive/clk-starfive-jhb100-per3.c new file mode 100644 index 000000000000..5533bb481f6d --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jhb100-per3.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JHB100 Peripheral-3 Clock Driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + * + */ + +#include +#include +#include +#include + +#include "clk-starfive-jhb100.h" + +#define JHB100_PER3CLK_NUM_CLKS (JHB100_PER3CLK_MAIN_ICG_EN_GMAC1 + 1) + +/* external clocks */ +#define JHB100_PER3CLK_100 (JHB100_PER3CLK_NUM_CLKS + 0) +#define JHB100_PER3CLK_125 (JHB100_PER3CLK_NUM_CLKS + 1) +#define JHB100_PER3CLK_600 (JHB100_PER3CLK_NUM_CLKS + 2) +#define JHB100_PER3CLK_OSC (JHB100_PER3CLK_NUM_CLKS + 3) +#define JHB100_PER3CLK_GMAC0_RMII_RCLKI (JHB100_PER3CLK_NUM_CLKS + 4) +#define JHB100_PER3CLK_GMAC1_SGMII_TX (JHB100_PER3CLK_NUM_CLKS + 5) +#define JHB100_PER3CLK_GMAC1_SGMII_RX (JHB100_PER3CLK_NUM_CLKS + 6) + +static const struct starfive_clk_data jhb100_per3crg_clk_data[] = { + STARFIVE__DIV(JHB100_PER3CLK_300, "per3_300", 256, + JHB100_PER3CLK_600), + STARFIVE__DIV(JHB100_PER3CLK_200, "per3_200", 256, + JHB100_PER3CLK_600), + STARFIVE__DIV(JHB100_PER3CLK_GMAC1_PTP_REF, "gmac1_ptp_ref", 2, + JHB100_PER3CLK_100), + STARFIVE__MUX(JHB100_PER3CLK_GMAC1_TX_125_MUX, "gmac1_tx_125_mux", 0, 2, + JHB100_PER3CLK_GMAC1_SGMII_TX, + JHB100_PER3CLK_125), + STARFIVE__DIV(JHB100_PER3CLK_GMAC1_TX, "gmac1_tx", 50, + JHB100_PER3CLK_GMAC1_TX_125_MUX), + STARFIVE__MUX(JHB100_PER3CLK_GMAC1_RX_125_MUX, "gmac1_rx_125_mux", 0, 2, + JHB100_PER3CLK_GMAC1_SGMII_RX, + JHB100_PER3CLK_125), + STARFIVE__DIV(JHB100_PER3CLK_GMAC1_RX, "gmac1_rx", 50, + JHB100_PER3CLK_GMAC1_RX_125_MUX), + STARFIVE__DIV(JHB100_PER3CLK_GMAC0_PTP_REF, "gmac0_ptp_ref", 2, + JHB100_PER3CLK_100), + STARFIVE__DIV(JHB100_PER3CLK_GMAC0_RMII_PLL, "gmac0_rmii_pll", 2, + JHB100_PER3CLK_100), + STARFIVE__MUX(JHB100_PER3CLK_GMAC0_RMII_MUX, "gmac0_rmii_mux", 0, 2, + JHB100_PER3CLK_GMAC0_RMII_PLL, + JHB100_PER3CLK_GMAC0_RMII_RCLKI), + STARFIVE__DIV(JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2, "gmac0_rmii_mux_div2", 20, + JHB100_PER3CLK_GMAC0_RMII_MUX), + STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_TX_I, "ether0_rmii_clk_tx_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2), + STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_RX_I, "ether0_rmii_clk_rx_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2), + STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_PTP_REF_I, "ether0_rmii_clk_ptp_ref_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_PTP_REF), + STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_RMII_I, "ether0_rmii_clk_rmii_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX), + STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_CSR_I, "ether0_rmii_clk_csr_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_100), + STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_ACLK_I, "ether0_rmii_aclk_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_300), + STARFIVE_GATE(JHB100_PER3CLK_GMAC0_RMII_RCLKO, "gmac0_rmii_rclko", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_PLL), + STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_I, "ether0_sgmii_clk_tx_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_TX), + STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_I, "ether0_sgmii_clk_rx_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_RX), + STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_125_I, "ether0_sgmii_clk_tx_125_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_TX_125_MUX), + STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_125_I, "ether0_sgmii_clk_rx_125_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_RX_125_MUX), + STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_PTP_REF_I, "ether0_sgmii_clk_ptp_ref_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_PTP_REF), + STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_REF_25_I, "ether0_sgmii_clk_ref_25_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_OSC), + STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_CSR_I, "ether0_sgmii_clk_csr_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_100), + STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_ACLK_I, "ether0_sgmii_aclk_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_300), + STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_PHY_PCLK_I, "ether0_sgmii_phy_pclk_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_100), + STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_SENSORS_PERIPH3, "main_icg_en_sensors_periph3", 0, + JHB100_PER3CLK_100), + STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_PECI0, "main_icg_en_peci0", 0, + JHB100_PER3CLK_100), + STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_PECI1, "main_icg_en_peci1", 0, + JHB100_PER3CLK_100), + STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_GMAC0, "main_icg_en_gmac0", + CLK_IS_CRITICAL, JHB100_PER3CLK_100), + STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_GMAC1, "main_icg_en_gmac1", + CLK_IS_CRITICAL, JHB100_PER3CLK_100), +}; + +static int jhb100_per3crg_probe(struct platform_device *pdev) +{ + struct starfive_clk_priv *priv; + unsigned int idx; + int ret; + + priv = devm_kzalloc(&pdev->dev, + struct_size(priv, reg, JHB100_PER3CLK_NUM_CLKS), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + spin_lock_init(&priv->rmw_lock); + priv->num_reg = JHB100_PER3CLK_NUM_CLKS; + priv->dev = &pdev->dev; + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + for (idx = 0; idx < JHB100_PER3CLK_NUM_CLKS; idx++) { + u32 max = jhb100_per3crg_clk_data[idx].max; + struct clk_parent_data parents[4] = {}; + struct clk_init_data init = { + .name = jhb100_per3crg_clk_data[idx].name, + .ops = starfive_clk_ops(max), + .parent_data = parents, + .num_parents = + ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1, + .flags = jhb100_per3crg_clk_data[idx].flags, + }; + struct starfive_clk *clk = &priv->reg[idx]; + unsigned int i; + + if (!init.name) + continue; + + for (i = 0; i < init.num_parents; i++) { + unsigned int pidx = jhb100_per3crg_clk_data[idx].parents[i]; + + if (pidx < JHB100_PER3CLK_NUM_CLKS) + parents[i].hw = &priv->reg[pidx].hw; + else if (pidx == JHB100_PER3CLK_100) + parents[i].fw_name = "per3_100"; + else if (pidx == JHB100_PER3CLK_125) + parents[i].fw_name = "per3_125"; + else if (pidx == JHB100_PER3CLK_600) + parents[i].fw_name = "per3_600"; + else if (pidx == JHB100_PER3CLK_OSC) + parents[i].fw_name = "osc"; + else if (pidx == JHB100_PER3CLK_GMAC0_RMII_RCLKI) + parents[i].fw_name = "per3_gmac0_rmii_rclki"; + else if (pidx == JHB100_PER3CLK_GMAC1_SGMII_TX) + parents[i].fw_name = "per3_gmac1_sgmii_tx"; + else if (pidx == JHB100_PER3CLK_GMAC1_SGMII_RX) + parents[i].fw_name = "per3_gmac1_sgmii_rx"; + } + + clk->hw.init = &init; + clk->idx = idx; + clk->max_div = max & STARFIVE_CLK_DIV_MASK; + + ret = devm_clk_hw_register(&pdev->dev, &clk->hw); + if (ret) + return ret; + } + + ret = devm_of_clk_add_hw_provider(&pdev->dev, starfive_clk_get, priv); + if (ret) + return ret; + + return jhb100_reset_controller_register(priv, "r-per3", 0); +} + +static const struct of_device_id jhb100_per3crg_match[] = { + { .compatible = "starfive,jhb100-per3crg" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jhb100_per3crg_match); + +static struct platform_driver jhb100_per3crg_driver = { + .probe = jhb100_per3crg_probe, + .driver = { + .name = "clk-starfive-jhb100-per3", + .of_match_table = jhb100_per3crg_match, + }, +}; +module_platform_driver(jhb100_per3crg_driver); + +MODULE_AUTHOR("Changhuang Liang "); +MODULE_DESCRIPTION("StarFive JHB100 Peripheral-3 Clock Driver"); +MODULE_LICENSE("GPL"); -- 2.25.1