IPQ5424 integrates the same PPE switch core as IPQ9574, but requires a different, smaller set of interconnect paths, and has only 3 front panel ports plus the EDMA FIFO interface, without the EIP FIFO. Add the IPQ5424 compatible, describe the interconnect paths of each SoC, and limit the Ethernet ports of IPQ5424 to ports 1-3. Signed-off-by: Luo Jie --- .../devicetree/bindings/net/qcom,ipq9574-ppe.yaml | 87 +++++++++++++++++----- 1 file changed, 70 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml index c899f4b56945..e5d218fc5d82 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml @@ -74,9 +74,14 @@ description: | +------->| QCA8075 PHY | | PHY4 | | PHY5 | (clock) +-------------------------------------+ +-------+ +-------+ + The IPQ5424 PPE reuses the same switch core, but wires up only 3 + front panel ports (GMAC0-2) and the single EDMA FIFO interface; it + has no EIP FIFO and no ports 4-6. + properties: compatible: enum: + - qcom,ipq5424-ppe - qcom,ipq9574-ppe reg: @@ -105,24 +110,16 @@ properties: description: PPE switch miscellaneous interrupt interconnects: - items: - - description: Bus interconnect path leading to PPE switch core function - - description: Bus interconnect path leading to PPE register access - - description: Bus interconnect path leading to QoS generation - - description: Bus interconnect path leading to timeout reference - - description: Bus interconnect path leading to NSS NOC from memory NOC - - description: Bus interconnect path leading to memory NOC from NSS NOC - - description: Bus interconnect path leading to enhanced memory NOC from NSS NOC + minItems: 5 + maxItems: 7 + description: + The number of interconnect paths depends on compatible, 5 paths for + qcom,ipq5424-ppe and 7 paths for qcom,ipq9574-ppe, enumerated in the + allOf conditionals below. interconnect-names: - items: - - const: ppe - - const: ppe_cfg - - const: qos_gen - - const: timeout_ref - - const: nssnoc_memnoc - - const: memnoc_nssnoc - - const: memnoc_nssnoc_1 + minItems: 5 + maxItems: 7 ethernet-dma: type: object @@ -182,7 +179,7 @@ properties: ethernet-ports: patternProperties: - "^ethernet-port@[1-6]+$": + "^ethernet-port@[1-6]$": type: object unevaluatedProperties: false $ref: ethernet-switch-port.yaml# @@ -236,6 +233,62 @@ required: allOf: - $ref: ethernet-switch.yaml + - if: + properties: + compatible: + contains: + const: qcom,ipq9574-ppe + then: + properties: + interconnects: + items: + - description: Bus interconnect path leading to PPE switch core function + - description: Bus interconnect path leading to PPE register access + - description: Bus interconnect path leading to QoS generation + - description: Bus interconnect path leading to timeout reference + - description: Bus interconnect path leading to NSS NOC from memory NOC + - description: Bus interconnect path leading to memory NOC from NSS NOC + - description: Bus interconnect path leading to enhanced memory NOC from NSS NOC + + interconnect-names: + items: + - const: ppe + - const: ppe_cfg + - const: qos_gen + - const: timeout_ref + - const: nssnoc_memnoc + - const: memnoc_nssnoc + - const: memnoc_nssnoc_1 + - if: + properties: + compatible: + contains: + const: qcom,ipq5424-ppe + then: + properties: + interconnects: + items: + - description: Bus interconnect path leading to PPE switch core function + - description: Bus interconnect path leading to PPE register access + - description: Bus interconnect path leading to CE AXI + - description: Bus interconnect path leading to CE APB + - description: Bus interconnect path leading to NSS CSR access + + interconnect-names: + items: + - const: ppe + - const: ppe_cfg + - const: nssnoc_ce_axi + - const: nssnoc_ce_apb + - const: nssnoc_nss_csr + + ethernet-ports: + patternProperties: + "^ethernet-port@[1-3]$": + properties: + reg: + maximum: 3 + "^ethernet-port@[4-6]$": false unevaluatedProperties: false -- 2.43.0