The alpha value of the Zonda PLLs is signed, so for a rate with a fractional part of one half or more, clk_zonda_pll_set_rate() programs L as the integer part rounded up, through zonda_pll_adjust_l_val(). Since commit a4d89b11aca3 ("clk: qcom: clk-alpha-pll: Simplify the zonda_pll_adjust_l_val()"), that function adds the rounding to the requested rate instead of to its quotient by the parent rate, so such a rate change writes the rate in Hz, truncated to 32 bits, into the L register. Use the quotient again. Fixes: a4d89b11aca3 ("clk: qcom: clk-alpha-pll: Simplify the zonda_pll_adjust_l_val()") Cc: stable@vger.kernel.org Signed-off-by: Abel Vesa --- Prepared with help from an LLM-based assistant. --- drivers/clk/qcom/clk-alpha-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 60173b076cc5..9782fb062a58 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -2271,7 +2271,7 @@ static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 quotient = rate; remainder = do_div(quotient, prate); - *l = rate + (u32)(remainder * 2 >= prate); + *l = quotient + (u32)(remainder * 2 >= prate); } static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, --- base-commit: 2637bdec0535a2044cd830eba9a79363651d9043 change-id: 20261103-clk-qcom-zonda-l-value-7f003397039d Best regards, -- Abel