cid.bpf.h explains its hand-rolled cmpxchg loop by saying the x86 BPF JIT rejects BPF_OR | BPF_FETCH and BPF_AND | BPF_FETCH on arena pointers, and names bpf_jit_supports_insn() as the place that does it. That function no longer rejects anything, so the comment sends the reader to code that contradicts it. The loop itself still has to stay: arm64 without LSE rejects every arena read-modify-write atomic. Reword the comment to say that instead. Signed-off-by: Puranjay Mohan --- tools/sched_ext/include/scx/cid.bpf.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/sched_ext/include/scx/cid.bpf.h b/tools/sched_ext/include/scx/cid.bpf.h index 69fb4e97bc771..41060dcf5f5f2 100644 --- a/tools/sched_ext/include/scx/cid.bpf.h +++ b/tools/sched_ext/include/scx/cid.bpf.h @@ -130,10 +130,10 @@ static __always_inline bool cmask_test(u32 cid, const struct scx_cmask __arena * } /* - * x86 BPF JIT rejects BPF_OR | BPF_FETCH and BPF_AND | BPF_FETCH on arena - * pointers (see bpf_jit_supports_insn() in arch/x86/net/bpf_jit_comp.c). Only - * BPF_CMPXCHG / BPF_XCHG / BPF_ADD with FETCH are allowed. Implement - * test_and_{set,clear} and the atomic set/clear via a cmpxchg loop. + * Not every BPF JIT accepts BPF_OR | BPF_FETCH and BPF_AND | BPF_FETCH on + * arena pointers: arm64 without LSE rejects every arena read-modify-write + * atomic. Implement test_and_{set,clear} and the atomic set/clear via a + * cmpxchg loop so this works everywhere. * * CMASK_CAS_TRIES is sized so exhausting it means seconds of real spinning * on one word - past any plausible contention. Abort hard. -- 2.53.0-Meta