From: Jiakai Xu Extend the documentation of guest supervisor-mode CSRs to include scounteren and senvcfg. These registers are part of the RISC-V supervisor CSR set but were previously missing from the documented encoding table. Also adjust the table formatting to keep column alignment consistent. Signed-off-by: Jiakai Xu --- Documentation/virt/kvm/api.rst | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index 01a3abef8abb..6dab20637c7b 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -2837,19 +2837,21 @@ of a Guest VCPU and it has the following id bit patterns:: Following are the RISC-V csr registers: -======================= ========= ============================================= - Encoding Register Description -======================= ========= ============================================= - 0x80x0 0000 0300 0000 sstatus Supervisor status - 0x80x0 0000 0300 0001 sie Supervisor interrupt enable - 0x80x0 0000 0300 0002 stvec Supervisor trap vector base - 0x80x0 0000 0300 0003 sscratch Supervisor scratch register - 0x80x0 0000 0300 0004 sepc Supervisor exception program counter - 0x80x0 0000 0300 0005 scause Supervisor trap cause - 0x80x0 0000 0300 0006 stval Supervisor bad address or instruction - 0x80x0 0000 0300 0007 sip Supervisor interrupt pending - 0x80x0 0000 0300 0008 satp Supervisor address translation and protection -======================= ========= ============================================= +======================= ========== ============================================= + Encoding Register Description +======================= ========== ============================================= + 0x80x0 0000 0300 0000 sstatus Supervisor status + 0x80x0 0000 0300 0001 sie Supervisor interrupt enable + 0x80x0 0000 0300 0002 stvec Supervisor trap vector base + 0x80x0 0000 0300 0003 sscratch Supervisor scratch register + 0x80x0 0000 0300 0004 sepc Supervisor exception program counter + 0x80x0 0000 0300 0005 scause Supervisor trap cause + 0x80x0 0000 0300 0006 stval Supervisor bad address or instruction + 0x80x0 0000 0300 0007 sip Supervisor interrupt pending + 0x80x0 0000 0300 0008 satp Supervisor address translation and protection + 0x80x0 0000 0300 0009 scounteren Supervisor counter-enable + 0x80x0 0000 0300 000a senvcfg Supervisor environment configuration +======================= ========== ============================================= RISC-V timer registers represent the timer state of a Guest VCPU and it has the following id bit patterns:: -- 2.34.1