Migrate to new vmx.h's pin based VM-execution controls, which makes it easier to grok from one code base to another. No functional change intended. Signed-off-by: Jon Kohler --- x86/vmx.c | 4 +- x86/vmx.h | 8 ---- x86/vmx_tests.c | 125 +++++++++++++++++++++++++++--------------------- 3 files changed, 74 insertions(+), 63 deletions(-) diff --git a/x86/vmx.c b/x86/vmx.c index dc52efa7..25a8d9f8 100644 --- a/x86/vmx.c +++ b/x86/vmx.c @@ -1254,7 +1254,9 @@ int init_vmcs(struct vmcs **vmcs) /* All settings to pin/exit/enter/cpu control fields should be placed here */ - ctrl_pin |= PIN_EXTINT | PIN_NMI | PIN_VIRT_NMI; + ctrl_pin |= PIN_BASED_EXT_INTR_MASK | + PIN_BASED_NMI_EXITING | + PIN_BASED_VIRTUAL_NMIS; ctrl_exit = EXI_LOAD_EFER | EXI_HOST_64 | EXI_LOAD_PAT; ctrl_enter = (ENT_LOAD_EFER | ENT_GUEST_64); /* DIsable IO instruction VMEXIT now */ diff --git a/x86/vmx.h b/x86/vmx.h index 36e784a7..e0e23ab6 100644 --- a/x86/vmx.h +++ b/x86/vmx.h @@ -427,14 +427,6 @@ enum Ctrl_ent { ENT_LOAD_BNDCFGS = 1UL << 16 }; -enum Ctrl_pin { - PIN_EXTINT = 1ul << 0, - PIN_NMI = 1ul << 3, - PIN_VIRT_NMI = 1ul << 5, - PIN_PREEMPT = 1ul << 6, - PIN_POST_INTR = 1ul << 7, -}; - enum Intr_type { VMX_INTR_TYPE_EXT_INTR = 0, VMX_INTR_TYPE_NMI_INTR = 2, diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c index ba50f2ee..1ea5d35b 100644 --- a/x86/vmx_tests.c +++ b/x86/vmx_tests.c @@ -128,11 +128,12 @@ u64 saved_rip; static int preemption_timer_init(struct vmcs *vmcs) { - if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { + if (!(ctrl_pin_rev.clr & PIN_BASED_VMX_PREEMPTION_TIMER)) { printf("\tPreemption timer is not supported\n"); return VMX_TEST_EXIT; } - vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); + vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | + PIN_BASED_VMX_PREEMPTION_TIMER); preempt_val = 10000000; vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; @@ -194,7 +195,8 @@ static int preemption_timer_exit_handler(union exit_reason exit_reason) "preemption timer during hlt"); vmx_set_test_stage(4); vmcs_write(PIN_CONTROLS, - vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); + vmcs_read(PIN_CONTROLS) & + ~PIN_BASED_VMX_PREEMPTION_TIMER); vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); @@ -236,7 +238,8 @@ static int preemption_timer_exit_handler(union exit_reason exit_reason) /* fall through */ case 4: vmcs_write(PIN_CONTROLS, - vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); + vmcs_read(PIN_CONTROLS) | + PIN_BASED_VMX_PREEMPTION_TIMER); vmcs_write(PREEMPT_TIMER_VALUE, 0); saved_rip = guest_rip + insn_len; return VMX_TEST_RESUME; @@ -255,7 +258,8 @@ static int preemption_timer_exit_handler(union exit_reason exit_reason) report_fail("Unknown exit reason, 0x%x", exit_reason.full); print_vmexit_info(exit_reason); } - vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); + vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & + ~PIN_BASED_VMX_PREEMPTION_TIMER); return VMX_TEST_VMEXIT; } @@ -1618,7 +1622,8 @@ static void timer_isr(isr_regs_t *regs) static int interrupt_init(struct vmcs *vmcs) { msr_bmp_init(); - vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); + vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & + ~PIN_BASED_EXT_INTR_MASK); handle_irq(TIMER_VECTOR, timer_isr); return VMX_TEST_START; } @@ -1727,17 +1732,20 @@ static int interrupt_exit_handler(union exit_reason exit_reason) case 2: case 5: vmcs_write(PIN_CONTROLS, - vmcs_read(PIN_CONTROLS) | PIN_EXTINT); + vmcs_read(PIN_CONTROLS) | + PIN_BASED_EXT_INTR_MASK); break; case 7: vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); vmcs_write(PIN_CONTROLS, - vmcs_read(PIN_CONTROLS) | PIN_EXTINT); + vmcs_read(PIN_CONTROLS) | + PIN_BASED_EXT_INTR_MASK); break; case 1: case 3: vmcs_write(PIN_CONTROLS, - vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); + vmcs_read(PIN_CONTROLS) & + ~PIN_BASED_EXT_INTR_MASK); break; case 4: case 6: @@ -1788,9 +1796,9 @@ static int nmi_hlt_init(struct vmcs *vmcs) msr_bmp_init(); handle_irq(NMI_VECTOR, nmi_isr); vmcs_write(PIN_CONTROLS, - vmcs_read(PIN_CONTROLS) & ~PIN_NMI); + vmcs_read(PIN_CONTROLS) & ~PIN_BASED_NMI_EXITING); vmcs_write(PIN_CONTROLS, - vmcs_read(PIN_CONTROLS) & ~PIN_VIRT_NMI); + vmcs_read(PIN_CONTROLS) & ~PIN_BASED_VIRTUAL_NMIS); return VMX_TEST_START; } @@ -1860,9 +1868,9 @@ static int nmi_hlt_exit_handler(union exit_reason exit_reason) } vmcs_write(PIN_CONTROLS, - vmcs_read(PIN_CONTROLS) | PIN_NMI); + vmcs_read(PIN_CONTROLS) | PIN_BASED_NMI_EXITING); vmcs_write(PIN_CONTROLS, - vmcs_read(PIN_CONTROLS) | PIN_VIRT_NMI); + vmcs_read(PIN_CONTROLS) | PIN_BASED_VIRTUAL_NMIS); vmcs_write(GUEST_RIP, guest_rip + insn_len); break; @@ -4053,7 +4061,7 @@ static void test_virtual_intr_ctls(void) u32 pin = saved_pin; if (!((ctrl_cpu_rev[1].clr & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) && - (ctrl_pin_rev.clr & PIN_EXTINT))) + (ctrl_pin_rev.clr & PIN_BASED_EXT_INTR_MASK))) return; vmcs_write(CPU_EXEC_CTRL0, @@ -4061,7 +4069,7 @@ static void test_virtual_intr_ctls(void) CPU_BASED_TPR_SHADOW); vmcs_write(CPU_EXEC_CTRL1, secondary & ~SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); - vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); + vmcs_write(PIN_CONTROLS, pin & ~PIN_BASED_EXT_INTR_MASK); report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); test_vmx_valid_controls(); report_prefix_pop(); @@ -4072,12 +4080,12 @@ static void test_virtual_intr_ctls(void) test_vmx_invalid_controls(); report_prefix_pop(); - vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); + vmcs_write(PIN_CONTROLS, pin | PIN_BASED_EXT_INTR_MASK); report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); test_vmx_valid_controls(); report_prefix_pop(); - vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); + vmcs_write(PIN_CONTROLS, pin & ~PIN_BASED_EXT_INTR_MASK); report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); test_vmx_invalid_controls(); report_prefix_pop(); @@ -4124,9 +4132,9 @@ static void test_posted_intr(void) u16 vec; int i; - if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && - (ctrl_cpu_rev[1].clr & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) && - (ctrl_exit_rev.clr & EXI_INTA))) + if (!((ctrl_pin_rev.clr & PIN_BASED_POSTED_INTR) && + (ctrl_cpu_rev[1].clr & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) && + (ctrl_exit_rev.clr & EXI_INTA))) return; vmcs_write(CPU_EXEC_CTRL0, @@ -4136,7 +4144,7 @@ static void test_posted_intr(void) /* * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit */ - pin |= PIN_POST_INTR; + pin |= PIN_BASED_POSTED_INTR; vmcs_write(PIN_CONTROLS, pin); secondary &= ~SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; vmcs_write(CPU_EXEC_CTRL1, secondary); @@ -4777,8 +4785,9 @@ static void test_nmi_ctrls(void) { u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; - if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != - (PIN_NMI | PIN_VIRT_NMI)) { + if ((ctrl_pin_rev.clr & + (PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS)) != + (PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS)) { report_skip("%s : NMI exiting and/or Virtual NMIs not supported", __func__); return; } @@ -4787,7 +4796,7 @@ static void test_nmi_ctrls(void) pin_ctrls = vmcs_read(PIN_CONTROLS); cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); - test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); + test_pin_ctrls = pin_ctrls & ~(PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS); test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_BASED_NMI_WINDOW_EXITING; vmcs_write(PIN_CONTROLS, test_pin_ctrls); @@ -4795,17 +4804,19 @@ static void test_nmi_ctrls(void) test_vmx_valid_controls(); report_prefix_pop(); - vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); + vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_BASED_VIRTUAL_NMIS); report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); test_vmx_invalid_controls(); report_prefix_pop(); - vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); + vmcs_write(PIN_CONTROLS, + test_pin_ctrls | (PIN_BASED_NMI_EXITING | + PIN_BASED_VIRTUAL_NMIS)); report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); test_vmx_valid_controls(); report_prefix_pop(); - vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); + vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_BASED_NMI_EXITING); report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); test_vmx_valid_controls(); report_prefix_pop(); @@ -4828,14 +4839,16 @@ static void test_nmi_ctrls(void) test_vmx_valid_controls(); report_prefix_pop(); - vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); + vmcs_write(PIN_CONTROLS, test_pin_ctrls | + (PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS)); vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_BASED_NMI_WINDOW_EXITING); report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); test_vmx_valid_controls(); report_prefix_pop(); - vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); + vmcs_write(PIN_CONTROLS, test_pin_ctrls | + (PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS)); vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); test_vmx_valid_controls(); @@ -5101,12 +5114,12 @@ static void test_vmx_preemption_timer(void) u32 exit = saved_exit; if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || - (ctrl_pin_rev.clr & PIN_PREEMPT))) { + (ctrl_pin_rev.clr & PIN_BASED_VMX_PREEMPTION_TIMER))) { report_skip("%s : \"Save-VMX-preemption-timer\" and/or \"Enable-VMX-preemption-timer\" control not supported", __func__); return; } - pin |= PIN_PREEMPT; + pin |= PIN_BASED_VMX_PREEMPTION_TIMER; vmcs_write(PIN_CONTROLS, pin); exit &= ~EXI_SAVE_PREEMPT; vmcs_write(EXI_CONTROLS, exit); @@ -5120,7 +5133,7 @@ static void test_vmx_preemption_timer(void) test_vmx_valid_controls(); report_prefix_pop(); - pin &= ~PIN_PREEMPT; + pin &= ~PIN_BASED_VMX_PREEMPTION_TIMER; vmcs_write(PIN_CONTROLS, pin); report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); test_vmx_invalid_controls(); @@ -6294,7 +6307,7 @@ static bool cpu_has_apicv(void) { return ((ctrl_cpu_rev[1].clr & SECONDARY_EXEC_APIC_REGISTER_VIRT) && (ctrl_cpu_rev[1].clr & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) && - (ctrl_pin_rev.clr & PIN_POST_INTR)); + (ctrl_pin_rev.clr & PIN_BASED_POSTED_INTR)); } /* Validates APIC register access across valid virtualization configurations. */ @@ -8665,7 +8678,7 @@ static void vmx_pending_event_test_core(bool guest_hlt) vmx_pending_event_guest_run = false; test_set_guest(vmx_pending_event_guest); - vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); + vmcs_set_bits(PIN_CONTROLS, PIN_BASED_EXT_INTR_MASK); enter_guest(); skip_exit_vmcall(); @@ -8739,7 +8752,7 @@ static void vmx_nmi_window_test(void) u64 nop_addr; void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); - if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { + if (!(ctrl_pin_rev.clr & PIN_BASED_VIRTUAL_NMIS)) { report_skip("%s : \"Virtual NMIs\" exec control not supported", __func__); return; } @@ -8753,7 +8766,7 @@ static void vmx_nmi_window_test(void) report_prefix_push("NMI-window"); test_set_guest(vmx_nmi_window_test_guest); - vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); + vmcs_set_bits(PIN_CONTROLS, PIN_BASED_VIRTUAL_NMIS); enter_guest(); skip_exit_vmcall(); nop_addr = vmcs_read(GUEST_RIP); @@ -9064,13 +9077,13 @@ static void vmx_preemption_timer_zero_test_guest(void) static void vmx_preemption_timer_zero_activate_preemption_timer(void) { - vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); + vmcs_set_bits(PIN_CONTROLS, PIN_BASED_VMX_PREEMPTION_TIMER); vmcs_write(PREEMPT_TIMER_VALUE, 0); } static void vmx_preemption_timer_zero_advance_past_vmcall(void) { - vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); + vmcs_clear_bits(PIN_CONTROLS, PIN_BASED_VMX_PREEMPTION_TIMER); enter_guest(); skip_exit_vmcall(); } @@ -9114,7 +9127,7 @@ static void vmx_preemption_timer_zero_test(void) handler old_db; u32 reason; - if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { + if (!(ctrl_pin_rev.clr & PIN_BASED_VMX_PREEMPTION_TIMER)) { report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); return; } @@ -9165,7 +9178,7 @@ static void vmx_preemption_timer_zero_test(void) report(reason == VMX_EXC_NMI, "Exit reason is 0x%x (expected 0x%x)", reason, VMX_EXC_NMI); - vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); + vmcs_clear_bits(PIN_CONTROLS, PIN_BASED_VMX_PREEMPTION_TIMER); enter_guest(); handle_exception(DB_VECTOR, old_db); @@ -9229,7 +9242,7 @@ static void vmx_preemption_timer_tf_test(void) u32 reason; int i; - if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { + if (!(ctrl_pin_rev.clr & PIN_BASED_VMX_PREEMPTION_TIMER)) { report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); return; } @@ -9243,7 +9256,7 @@ static void vmx_preemption_timer_tf_test(void) skip_exit_vmcall(); vmx_set_test_stage(1); - vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); + vmcs_set_bits(PIN_CONTROLS, PIN_BASED_VMX_PREEMPTION_TIMER); vmcs_write(PREEMPT_TIMER_VALUE, 50000); vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); @@ -9268,7 +9281,7 @@ static void vmx_preemption_timer_tf_test(void) report(reason == VMX_PREEMPT, "No single-step traps skipped"); vmx_set_test_stage(2); - vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); + vmcs_clear_bits(PIN_CONTROLS, PIN_BASED_VMX_PREEMPTION_TIMER); enter_guest(); handle_exception(DB_VECTOR, old_db); @@ -9320,7 +9333,7 @@ static void vmx_preemption_timer_expiry_test(void) u64 tsc_deadline; u32 reason; - if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { + if (!(ctrl_pin_rev.clr & PIN_BASED_VMX_PREEMPTION_TIMER)) { report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); return; } @@ -9334,7 +9347,7 @@ static void vmx_preemption_timer_expiry_test(void) preemption_timer_value = VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit; - vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); + vmcs_set_bits(PIN_CONTROLS, PIN_BASED_VMX_PREEMPTION_TIMER); vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value); vmx_set_test_stage(0); @@ -9349,7 +9362,7 @@ static void vmx_preemption_timer_expiry_test(void) "Last stored guest TSC (%lu) < TSC deadline (%lu)", vmx_preemption_timer_expiry_finish, tsc_deadline); - vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); + vmcs_clear_bits(PIN_CONTROLS, PIN_BASED_VMX_PREEMPTION_TIMER); vmx_set_test_stage(1); enter_guest(); } @@ -9570,7 +9583,7 @@ static void enable_vid(void) virtual_apic_page = alloc_page(); vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); - vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); + vmcs_set_bits(PIN_CONTROLS, PIN_BASED_EXT_INTR_MASK); vmcs_write(EOI_EXIT_BITMAP0, 0x0); vmcs_write(EOI_EXIT_BITMAP1, 0x0); @@ -9589,7 +9602,7 @@ static void enable_posted_interrupts(void) { void *pi_desc = alloc_page(); - vmcs_set_bits(PIN_CONTROLS, PIN_POST_INTR); + vmcs_set_bits(PIN_CONTROLS, PIN_BASED_POSTED_INTR); vmcs_set_bits(EXI_CONTROLS, EXI_INTA); vmcs_write(PINV, PI_VECTOR); vmcs_write(POSTED_INTR_DESC_ADDR, (u64)pi_desc); @@ -9761,7 +9774,8 @@ static void vmx_apic_passthrough(bool set_irq_line_from_thread) disable_intercept_for_x2apic_msrs(); - vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); + vmcs_write(PIN_CONTROLS, + vmcs_read(PIN_CONTROLS) & ~PIN_BASED_EXT_INTR_MASK); vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); @@ -9823,7 +9837,7 @@ static void vmx_apic_passthrough_tpr_threshold_test(void) int ipi_vector = 0xe1; disable_intercept_for_x2apic_msrs(); - vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); + vmcs_clear_bits(PIN_CONTROLS, PIN_BASED_EXT_INTR_MASK); /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ cli(); @@ -10094,7 +10108,8 @@ static void sipi_test_ap_thread(void *data) /* passthrough lapic to L2 */ disable_intercept_for_x2apic_msrs(); - vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); + vmcs_write(PIN_CONTROLS, + vmcs_read(PIN_CONTROLS) & ~PIN_BASED_EXT_INTR_MASK); vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); @@ -10146,7 +10161,8 @@ static void vmx_sipi_signal_test(void) /* passthrough lapic to L2 */ disable_intercept_for_x2apic_msrs(); - vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); + vmcs_write(PIN_CONTROLS, + vmcs_read(PIN_CONTROLS) & ~PIN_BASED_EXT_INTR_MASK); vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); @@ -10577,11 +10593,12 @@ static void rdtsc_vmexit_diff_test(void) static int invalid_msr_init(struct vmcs *vmcs) { - if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { + if (!(ctrl_pin_rev.clr & PIN_BASED_VMX_PREEMPTION_TIMER)) { printf("\tPreemption timer is not supported\n"); return VMX_TEST_EXIT; } - vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); + vmcs_write(PIN_CONTROLS, + vmcs_read(PIN_CONTROLS) | PIN_BASED_VMX_PREEMPTION_TIMER); preempt_val = 10000000; vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; -- 2.43.0