GICv5 requires a mapping of Interrupt AFFinity IDs to CPUs, and uses CPU Phandles in the FDT for this purpose. Create a per-CPU phandle when writing the CPU FDT nodes, which can then be used later on when generating the FDT to create this mapping of CPUs to their IAFFIDs. These CPU phandles come after those hard-coded for the GIC and MSE controller. Signed-off-by: Sascha Bischoff --- arm64/fdt.c | 3 +++ arm64/include/kvm/fdt-arch.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/arm64/fdt.c b/arm64/fdt.c index 98f1dd9d..44361e6b 100644 --- a/arm64/fdt.c +++ b/arm64/fdt.c @@ -54,6 +54,9 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm) _FDT(fdt_property_string(fdt, "enable-method", "psci")); _FDT(fdt_property_cell(fdt, "reg", mpidr)); + + _FDT(fdt_property_cell(fdt, "phandle", PHANDLE_CPU_BASE + cpu)); + _FDT(fdt_end_node(fdt)); } diff --git a/arm64/include/kvm/fdt-arch.h b/arm64/include/kvm/fdt-arch.h index 60c2d406..3c3bd682 100644 --- a/arm64/include/kvm/fdt-arch.h +++ b/arm64/include/kvm/fdt-arch.h @@ -3,4 +3,6 @@ enum phandles {PHANDLE_RESERVED = 0, PHANDLE_GIC, PHANDLE_MSI, PHANDLES_MAX}; +#define PHANDLE_CPU_BASE PHANDLES_MAX + #endif /* ARM__FDT_H */ -- 2.34.1