From: "Jan Petrous (OSS)" The example references the SerDes PHY as phys = <&serdes0 PHY_TYPE_PCIE 0 0>; i.e. the SerDes node itself with three PHY cells. That does not match the SerDes binding: the per-lane child node is the generic PHY provider and carries '#phy-cells = <0>', while the SerDes node itself has no '#phy-cells' at all. Point the example at the PCIe lane child instead, which is also what the S32G3 board device trees use. The dt-bindings/phy/phy.h include is dropped along with the now-unused PHY_TYPE_PCIE constant. The schema itself is unchanged; 'phys: maxItems: 1' already describes the corrected form. Signed-off-by: Jan Petrous (OSS) --- Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml b/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml index 66a050028278..29323e50bd8b 100644 --- a/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml @@ -82,7 +82,6 @@ unevaluatedProperties: false examples: - | #include - #include bus { #address-cells = <2>; @@ -124,7 +123,7 @@ examples: ranges; device_type = "pci"; - phys = <&serdes0 PHY_TYPE_PCIE 0 0>; + phys = <&serdes0_pcie0>; }; }; }; -- 2.55.0