From: Shangjuan Wei Add Ethernet controller support for Eswin's eic7700 SoC. The driver provides management and control of Ethernet signals for the eiC7700 series chips. Signed-off-by: Zhi Li Signed-off-by: Shangjuan Wei --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-eic7700.c | 270 ++++++++++++++++++ 3 files changed, 282 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 67fa879b1e52..a13b15ce1abd 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -67,6 +67,17 @@ config DWMAC_ANARION This selects the Anarion SoC glue layer support for the stmmac driver. +config DWMAC_EIC7700 + tristate "Support for Eswin eic7700 ethernet driver" + select CRC32 + select MII + depends on OF && HAS_DMA && ARCH_ESWIN || COMPILE_TEST + help + This driver supports the Eswin EIC7700 Ethernet controller, + which integrates Synopsys DesignWare QoS features. It enables + high-speed networking with DMA acceleration and is optimized + for embedded systems. + config DWMAC_INGENIC tristate "Ingenic MAC support" default MACH_INGENIC diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index b591d93f8503..f4ec5fc16571 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -14,6 +14,7 @@ stmmac-$(CONFIG_STMMAC_SELFTESTS) += stmmac_selftests.o # Ordering matters. Generic driver must be last. obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o obj-$(CONFIG_DWMAC_ANARION) += dwmac-anarion.o +obj-$(CONFIG_DWMAC_EIC7700) += dwmac-eic7700.o obj-$(CONFIG_DWMAC_INGENIC) += dwmac-ingenic.o obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c new file mode 100644 index 000000000000..8b2082126a42 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Eswin DWC Ethernet linux driver + * + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd. + * + * Authors: + * Zhi Li + * Shuang Liang + * Shangjuan Wei + */ + +#include +#include +#include +#include +#include + +#include "stmmac_platform.h" + +/* eth_phy_ctrl_offset eth0:0x100 */ +#define EIC7700_ETH_TX_CLK_SEL BIT(16) +#define EIC7700_ETH_PHY_INTF_SELI BIT(0) + +/* eth_axi_lp_ctrl_offset eth0:0x108 */ +#define EIC7700_ETH_CSYSREQ_VAL BIT(0) + +/* + * TX/RX Clock Delay Bit Masks: + * - TX Delay: bits [14:8] — TX_CLK delay (unit: 0.1ns per bit) + * - RX Delay: bits [30:24] — RX_CLK delay (unit: 0.1ns per bit) + */ +#define EIC7700_ETH_TX_ADJ_DELAY GENMASK(14, 8) +#define EIC7700_ETH_RX_ADJ_DELAY GENMASK(30, 24) + +#define EIC7700_MAX_DELAY_UNIT 0x7F + +struct eic7700_qos_priv { + struct device *dev; + struct regmap *hsp_regmap; + struct clk *clk_tx; + struct clk *clk_axi; + struct clk *clk_cfg; + u32 tx_delay_ps; + u32 rx_delay_ps; +}; + +/** + * eic7700_apply_delay - Update TX or RX delay bits in delay parameter value. + * @delay_ps: Delay in picoseconds (capped at 12.7ns). + * @reg: Pointer to register value to modify. + * @is_rx: True for RX delay (bits 30:24), false for TX delay (bits 14:8). + * + * Converts delay to 0.1ns units, caps at 0x7F, and sets appropriate bits. + * Only RX or TX bits are updated; other bits remain unchanged. + */ +static inline void eic7700_apply_delay(u32 delay_ps, u32 *reg, bool is_rx) +{ + if (!reg) + return; + + u32 val = min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT); + + if (is_rx) { + *reg &= ~EIC7700_ETH_RX_ADJ_DELAY; + *reg |= (val << 24) & EIC7700_ETH_RX_ADJ_DELAY; + } else { + *reg &= ~EIC7700_ETH_TX_ADJ_DELAY; + *reg |= (val << 8) & EIC7700_ETH_TX_ADJ_DELAY; + } +} + +static int eic7700_clks_config(void *priv, bool enabled) +{ + struct eic7700_qos_priv *dwc = (struct eic7700_qos_priv *)priv; + int ret = 0; + + if (enabled) { + ret = clk_prepare_enable(dwc->clk_tx); + if (ret < 0) { + dev_err(dwc->dev, "Failed to enable tx clock: %d\n", + ret); + goto err; + } + + ret = clk_prepare_enable(dwc->clk_axi); + if (ret < 0) { + dev_err(dwc->dev, "Failed to enable axi clock: %d\n", + ret); + goto err_tx; + } + + ret = clk_prepare_enable(dwc->clk_cfg); + if (ret < 0) { + dev_err(dwc->dev, "Failed to enable cfg clock: %d\n", + ret); + goto err_axi; + } + } else { + clk_disable_unprepare(dwc->clk_tx); + clk_disable_unprepare(dwc->clk_axi); + clk_disable_unprepare(dwc->clk_cfg); + } + return ret; + +err_axi: + clk_disable_unprepare(dwc->clk_axi); +err_tx: + clk_disable_unprepare(dwc->clk_tx); +err: + return ret; +} + +static int eic7700_dwmac_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct eic7700_qos_priv *dwc_priv; + u32 eth_axi_lp_ctrl_offset; + u32 eth_phy_ctrl_offset; + u32 eth_phy_ctrl_regset; + u32 eth_rxd_dly_offset; + u32 eth_dly_param = 0; + int ret; + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to get resources\n"); + + plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) + return dev_err_probe(&pdev->dev, PTR_ERR(plat_dat), + "dt configuration failed\n"); + + dwc_priv = devm_kzalloc(&pdev->dev, sizeof(*dwc_priv), GFP_KERNEL); + if (!dwc_priv) + return -ENOMEM; + + dwc_priv->dev = &pdev->dev; + + /* Read rx-internal-delay-ps and update rx_clk delay */ + if (!of_property_read_u32(pdev->dev.of_node, + "rx-internal-delay-ps", + &dwc_priv->rx_delay_ps)) { + eic7700_apply_delay(dwc_priv->rx_delay_ps, + ð_dly_param, true); + } else { + dev_warn(&pdev->dev, "can't get rx-internal-delay-ps\n"); + } + + /* Read tx-internal-delay-ps and update tx_clk delay */ + if (!of_property_read_u32(pdev->dev.of_node, + "tx-internal-delay-ps", + &dwc_priv->tx_delay_ps)) { + eic7700_apply_delay(dwc_priv->tx_delay_ps, + ð_dly_param, false); + } else { + dev_warn(&pdev->dev, "can't get tx-internal-delay-ps\n"); + } + + dwc_priv->hsp_regmap = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "eswin,hsp-sp-csr"); + if (IS_ERR(dwc_priv->hsp_regmap)) + return dev_err_probe(&pdev->dev, + PTR_ERR(dwc_priv->hsp_regmap), + "Failed to get hsp-sp-csr regmap\n"); + + ret = of_property_read_u32_index(pdev->dev.of_node, + "eswin,hsp-sp-csr", + 1, ð_phy_ctrl_offset); + if (ret) + return dev_err_probe(&pdev->dev, + ret, + "can't get eth_phy_ctrl_offset\n"); + + regmap_read(dwc_priv->hsp_regmap, eth_phy_ctrl_offset, + ð_phy_ctrl_regset); + eth_phy_ctrl_regset |= + (EIC7700_ETH_TX_CLK_SEL | EIC7700_ETH_PHY_INTF_SELI); + regmap_write(dwc_priv->hsp_regmap, eth_phy_ctrl_offset, + eth_phy_ctrl_regset); + + ret = of_property_read_u32_index(pdev->dev.of_node, + "eswin,hsp-sp-csr", + 2, ð_axi_lp_ctrl_offset); + if (ret) + return dev_err_probe(&pdev->dev, + ret, + "can't get eth_axi_lp_ctrl_offset\n"); + + regmap_write(dwc_priv->hsp_regmap, eth_axi_lp_ctrl_offset, + EIC7700_ETH_CSYSREQ_VAL); + + ret = of_property_read_u32_index(pdev->dev.of_node, + "eswin,hsp-sp-csr", + 3, ð_rxd_dly_offset); + if (ret) + return dev_err_probe(&pdev->dev, + ret, + "can't get eth_rxd_dly_offset\n"); + + regmap_write(dwc_priv->hsp_regmap, eth_rxd_dly_offset, + eth_dly_param); + + dwc_priv->clk_tx = devm_clk_get(&pdev->dev, "tx"); + if (IS_ERR(dwc_priv->clk_tx)) + return dev_err_probe(&pdev->dev, + PTR_ERR(dwc_priv->clk_tx), + "error getting tx clock\n"); + + dwc_priv->clk_axi = devm_clk_get(&pdev->dev, "axi"); + if (IS_ERR(dwc_priv->clk_axi)) + return dev_err_probe(&pdev->dev, + PTR_ERR(dwc_priv->clk_axi), + "error getting axi clock\n"); + + dwc_priv->clk_cfg = devm_clk_get(&pdev->dev, "cfg"); + if (IS_ERR(dwc_priv->clk_cfg)) + return dev_err_probe(&pdev->dev, + PTR_ERR(dwc_priv->clk_cfg), + "error getting cfg clock\n"); + + ret = eic7700_clks_config(dwc_priv, true); + if (ret) + return dev_err_probe(&pdev->dev, + ret, + "error enable clock\n"); + + plat_dat->clk_tx_i = dwc_priv->clk_tx; + plat_dat->set_clk_tx_rate = stmmac_set_clk_tx_rate; + plat_dat->bsp_priv = dwc_priv; + plat_dat->clks_config = eic7700_clks_config; + + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) { + eic7700_clks_config(dwc_priv, false); + return dev_err_probe(&pdev->dev, + ret, + "Failed to driver probe\n"); + } + + return ret; +} + +static void eic7700_dwmac_remove(struct platform_device *pdev) +{ + struct eic7700_qos_priv *dwc_priv = get_stmmac_bsp_priv(&pdev->dev); + + stmmac_pltfr_remove(pdev); + eic7700_clks_config(dwc_priv, false); +} + +static const struct of_device_id eic7700_dwmac_match[] = { + { .compatible = "eswin,eic7700-qos-eth" }, + { } +}; +MODULE_DEVICE_TABLE(of, eic7700_dwmac_match); + +static struct platform_driver eic7700_dwmac_driver = { + .probe = eic7700_dwmac_probe, + .remove = eic7700_dwmac_remove, + .driver = { + .name = "eic7700-eth-dwmac", + .pm = &stmmac_pltfr_pm_ops, + .of_match_table = eic7700_dwmac_match, + }, +}; +module_platform_driver(eic7700_dwmac_driver); + +MODULE_AUTHOR("Zhi Li "); +MODULE_AUTHOR("Shuang Liang "); +MODULE_AUTHOR("Shangjuan Wei "); +MODULE_DESCRIPTION("Eswin eic7700 qos ethernet driver"); +MODULE_LICENSE("GPL"); -- 2.17.1