A regression was reported on an AMD Ryzen AI HX 370 running a cache intensive Clang full-LTO link. The little cores run at a much lower frequency (3.3 GHz vs 5.1 GHz) and have only half of the L3 cache (8 MB vs 16 MB), so pinning such a task to the little-core LLC hurts twice, and full-LTO builds slow down dramatically compared to pre-cache-aware-scheduling kernels. Asym packing and cache aware scheduling express conflicting placement strategies. Asym packing wants a task to run on the highest priority CPU, whereas cache aware scheduling wants to co-locate the tasks of a process on one LLC regardless of the priority of CPUs in that LLC. When asym packing tries to migrate task to an idle core that has higher priority than source cpu, let asym packing win. Moving tasks to a higher performing idle core will buy more performance than cache co-location. Prioritize asym packing over LLC balancing for regular and active load balancing. Fixes: 23b2b5ccc45c ("sched/cache: Introduce helper functions to enforce LLC migration policy") Reported-by: Klaus Kusche Closes: https://lore.kernel.org/lkml/2180ea5a-eb28-4152-8d4d-cd00b0c24b2e@computerix.info/ Suggested-by: Kayra Cizmeci Reviewed-by: Kayra Cizmeci Tested-by: Klaus Kusche Tested-by: Ricardo Neri Tested-by: Chen Yu Cc: stable@vger.kernel.org # 7.2.x Signed-off-by: Tim Chen --- Notes: v3: Remove redundant SD_ASYM_PACKING check in llc_balance() (Kayra Cizmeci). Add Tested-by tag from Chen Yu and Reviewed-by tag from Kayra Cizmeci. Link v2: https://lore.kernel.org/lkml/77ceef1e51b895760dc5f6c9cde985a1679545b5.1791224900.git.tim.c.chen@linux.intel.com/ kernel/sched/fair.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 57360f5cdde4f..e4906486a4fe9 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -10934,6 +10934,8 @@ static inline bool task_misfits_asym_cpu(struct lb_env *env, struct task_struct return false; } +static inline bool sched_asym(struct sched_domain *sd, int dst_cpu, int src_cpu); + /* * Check if task p can migrate from source LLC to * destination LLC in terms of cache aware load balance. @@ -10958,6 +10960,10 @@ static enum llc_mig can_migrate_llc_task(struct lb_env *env, if (cpu < 0 || cpus_share_cache(src_cpu, dst_cpu)) return mig_unrestricted; + /* Prioritize asym packing to idle core over cache awareness */ + if (env->idle && sched_asym(env->sd, dst_cpu, src_cpu)) + return mig_unrestricted; + /* skip cache aware load balance for too many threads */ if (invalid_llc_nr(grp, p, dst_cpu) || exceed_llc_capacity(grp, dst_cpu)) { @@ -12154,6 +12160,14 @@ static inline bool llc_balance(struct lb_env *env, struct sg_lb_stats *sgs, sgs->group_misfit_task_load) return false; + /* + * On asym packing domains, if the destination CPU + * has higher priority than all CPUs in the source group, + * prioritize asym packing. + */ + if (sgs->group_asym_packing) + return false; + /* * Skip cache aware tagging if nr_balanced_failed is sufficiently high. * Threshold of cache_nice_tries is set to 1 higher than nr_balance_failed @@ -13569,12 +13583,12 @@ static int need_active_balance(struct lb_env *env) { struct sched_domain *sd = env->sd; - if (alb_break_llc(env)) - return 0; - if (asym_active_balance(env)) return 1; + if (alb_break_llc(env)) + return 0; + if (imbalanced_active_balance(env)) return 1; -- 2.32.0