From: Shangjuan Wei Due to the detection of errors in the eswin mmc module regarding the eswin,hsp-sp-csr attributes in the eswin,eic7700-eth.yaml file, the link is as follows: https://lore.kernel.org/all/176096011380.22917.1988679321096076522.robh@kernel.org/ Therefore, the eswin,hsp-sp-csr attributes of the eic7700-eth.yaml file regarding eswin and hsp-sp-csr will be changed to the form of: items: - items: - description: ... - description: ... - description: ... - description: ... The MMC,Ethernet,and USB modules of eswin vendor have defined eswin,hsp-sp-csr attribute in YAML. In order to be consistent with the property description of MMC,USB, I have modified the description content of eswin,hsp-sp-csr attribute in Ethernet YAML. Fixes: 888bd0eca93c("dt-bindings: ethernet: eswin: Document for EIC7700 SoC") Reported-by: Rob Herring (Arm) Closes: https://lore.kernel.org/all/176096011380.22917.1988679321096076522.robh@kernel.org/ Signed-off-by: Shangjuan Wei --- .../bindings/net/eswin,eic7700-eth.yaml | 20 ++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml index 9ddbfe219ae2..91e8cd1db67b 100644 --- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml @@ -69,17 +69,19 @@ properties: enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400] eswin,hsp-sp-csr: + description: + HSP CSR is to control and get status of different high-speed peripherals + (such as Ethernet, USB, SATA, etc.) via register, which can tune + board-level's parameters of PHY, etc. $ref: /schemas/types.yaml#/definitions/phandle-array items: - - description: Phandle to HSP(High-Speed Peripheral) device - - description: Offset of phy control register for internal - or external clock selection - - description: Offset of AXI clock controller Low-Power request - register - - description: Offset of register controlling TX/RX clock delay - description: | - High-Speed Peripheral device needed to configure clock selection, - clock low-power mode and clock delay. + - items: + - description: Phandle to HSP(High-Speed Peripheral) device + - description: Offset of phy control register for internal + or external clock selection + - description: Offset of AXI clock controller Low-Power request + register + - description: Offset of register controlling TX/RX clock delay required: - compatible -- 2.17.1