Support to 5-bit register indices in VMCS fields when EGPRs are enabled. Signed-off-by: Chang S. Bae --- RFC note: The "chicken bit" (XCR0.APX) checker is intentionally deferred, as the emulator in the next series will do a similar check. Consolidating the XCR0 handling at the end keeps the logic clearer during the feature exposition. --- arch/x86/kvm/vmx/vmx.h | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index b8da6ebc35dc..6cf1eb739caf 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -374,12 +374,17 @@ struct vmx_insn_info { static inline bool vmx_egpr_enabled(struct kvm_vcpu *vcpu __maybe_unused) { return false; } -static inline struct vmx_insn_info vmx_get_insn_info(struct kvm_vcpu *vcpu __maybe_unused) +static inline struct vmx_insn_info vmx_get_insn_info(struct kvm_vcpu *vcpu) { struct vmx_insn_info insn; - insn.extended = false; - insn.info.word = vmcs_read32(VMX_INSTRUCTION_INFO); + if (vmx_egpr_enabled(vcpu)) { + insn.extended = true; + insn.info.dword = vmcs_read64(EXTENDED_INSTRUCTION_INFO); + } else { + insn.extended = false; + insn.info.word = vmcs_read32(VMX_INSTRUCTION_INFO); + } return insn; } @@ -415,7 +420,10 @@ static __always_inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu) static inline int vmx_get_exit_qual_gpr(struct kvm_vcpu *vcpu) { - return (vmx_get_exit_qual(vcpu) >> 8) & 0xf; + if (vmx_egpr_enabled(vcpu)) + return (vmx_get_exit_qual(vcpu) >> 8) & 0x1f; + else + return (vmx_get_exit_qual(vcpu) >> 8) & 0xf; } static __always_inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu) -- 2.51.0