From: "Jan Petrous (OSS)" Add the SCMI reset domain protocol (protocol@16) node under the SCMI firmware node for both S32G2 and S32G3, so that on-SoC controllers can request resets through the SCMI reset controller. The node is labelled scmi_reset rather than reset: a label that generic in a SoC .dtsi invites collisions and reads poorly at the use sites, and the sibling clock protocol node already uses the shortened clks form. Signed-off-by: Jan Petrous (OSS) --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 5 +++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 996494e34593..6a2774d53747 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -100,6 +100,11 @@ clks: protocol@14 { reg = <0x14>; #clock-cells = <1>; }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; }; psci { diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 31f7aad00b76..da3915b7e915 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -139,6 +139,11 @@ clks: protocol@14 { reg = <0x14>; #clock-cells = <1>; }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; }; psci: psci { -- 2.55.0