CN20K NPC MCAM is split into 32 subbanks that are searched in a predefined order during allocation. Lower-numbered subbanks have higher priority than higher-numbered ones. Add a runtime devlink parameter "srch_order" ( DEVLINK_PARAM_TYPE_U32_ARRAY) to control the order in which subbanks are searched during MCAM allocation. Signed-off-by: Ratheesh Kannoth --- .../ethernet/marvell/octeontx2/af/cn20k/npc.c | 70 ++++++++++++++ .../ethernet/marvell/octeontx2/af/cn20k/npc.h | 2 + .../marvell/octeontx2/af/rvu_devlink.c | 92 +++++++++++++++++-- 3 files changed, 154 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c index e854b85ced9e..7f014b414d68 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c @@ -3809,6 +3809,76 @@ static void npc_unlock_all_subbank(void) mutex_unlock(&npc_priv.sb[i].lock); } +int npc_cn20k_search_order_set(struct rvu *rvu, + u32 arr[MAX_NUM_SUB_BANKS], int cnt) +{ + struct npc_mcam *mcam = &rvu->hw->mcam; + u32 fslots[MAX_NUM_SUB_BANKS][2]; + u32 uslots[MAX_NUM_SUB_BANKS][2]; + int fcnt = 0, ucnt = 0; + struct npc_subbank *sb; + unsigned long index; + int idx, val; + void *v; + + if (cnt != npc_priv.num_subbanks) { + dev_err(rvu->dev, "Number of entries(%u) != %u\n", + cnt, npc_priv.num_subbanks); + return -EINVAL; + } + + npc_lock_all_subbank(); + mutex_lock(&mcam->lock); + restrict_valid = false; + + for (int i = 0; i < cnt; i++) + subbank_srch_order[i] = arr[i]; + + xa_for_each(&npc_priv.xa_sb_used, index, v) { + val = xa_to_value(v); + uslots[ucnt][0] = index; + uslots[ucnt][1] = val; + xa_erase(&npc_priv.xa_sb_used, index); + ucnt++; + } + + xa_for_each(&npc_priv.xa_sb_free, index, v) { + val = xa_to_value(v); + fslots[fcnt][0] = index; + fslots[fcnt][1] = val; + xa_erase(&npc_priv.xa_sb_free, index); + fcnt++; + } + + for (int i = 0; i < ucnt; i++) { + idx = uslots[i][1]; + sb = &npc_priv.sb[idx]; + sb->arr_idx = subbank_srch_order[sb->idx]; + xa_store(&npc_priv.xa_sb_used, sb->arr_idx, + xa_mk_value(sb->idx), GFP_KERNEL); + } + + for (int i = 0; i < fcnt; i++) { + idx = fslots[i][1]; + sb = &npc_priv.sb[idx]; + sb->arr_idx = subbank_srch_order[sb->idx]; + xa_store(&npc_priv.xa_sb_free, sb->arr_idx, + xa_mk_value(sb->idx), GFP_KERNEL); + } + + npc_unlock_all_subbank(); + mutex_unlock(&mcam->lock); + + return 0; +} + +const u32 *npc_cn20k_search_order_get(bool *restricted_order, u32 *sz) +{ + *restricted_order = restrict_valid; + *sz = npc_priv.num_subbanks; + return subbank_srch_order; +} + /* Only non-ref non-contigous mcam indexes * are picked for defrag process */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h index 004a556c7b90..b168ecfbc5c8 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h @@ -343,5 +343,7 @@ int npc_cn20k_defrag(struct rvu *rvu); int npc_mcam_idx_2_subbank_idx(struct rvu *rvu, u16 mcam_idx, struct npc_subbank **sb, int *sb_off); +const u32 *npc_cn20k_search_order_get(bool *restricted_order, u32 *sz); +int npc_cn20k_search_order_set(struct rvu *rvu, u32 arr[32], int cnt); #endif /* NPC_CN20K_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c index 287ff0eda152..420cda6d5d5f 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c @@ -1258,6 +1258,7 @@ enum rvu_af_dl_param_id { RVU_AF_DEVLINK_PARAM_ID_NPC_EXACT_FEATURE_DISABLE, RVU_AF_DEVLINK_PARAM_ID_NPC_DEF_RULE_CNTR_ENABLE, RVU_AF_DEVLINK_PARAM_ID_NPC_DEFRAG, + RVU_AF_DEVLINK_PARAM_ID_NPC_SRCH_ORDER, RVU_AF_DEVLINK_PARAM_ID_NIX_MAXLF, }; @@ -1619,12 +1620,83 @@ static int rvu_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, return 0; } +static int rvu_af_dl_npc_srch_order_set(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx, + struct netlink_ext_ack *extack) +{ + struct rvu_devlink *rvu_dl = devlink_priv(devlink); + struct rvu *rvu = rvu_dl->rvu; + + return npc_cn20k_search_order_set(rvu, + ctx->val.u32arr.val, + ctx->val.u32arr.size); +} + +static int rvu_af_dl_npc_srch_order_get(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx, + struct netlink_ext_ack *extack) +{ + bool restricted_order; + const u32 *order; + u32 sz; + + order = npc_cn20k_search_order_get(&restricted_order, &sz); + ctx->val.u32arr.size = sz; + for (int i = 0; i < sz; i++) + ctx->val.u32arr.val[i] = order[i]; + + return 0; +} + +static int rvu_af_dl_npc_srch_order_validate(struct devlink *devlink, u32 id, + union devlink_param_value val, + struct netlink_ext_ack *extack) +{ + struct rvu_devlink *rvu_dl = devlink_priv(devlink); + struct rvu *rvu = rvu_dl->rvu; + bool restricted_order; + unsigned long w = 0; + u32 *arr; + u32 sz; + + npc_cn20k_search_order_get(&restricted_order, &sz); + if (sz != val.u32arr.size) { + dev_err(rvu->dev, + "Wrong size %u, should be %u\n", + val.u32arr.size, sz); + return -EINVAL; + } + + arr = val.u32arr.val; + for (int i = 0; i < sz; i++) { + if (arr[i] >= sz) + return -EINVAL; + + w |= BIT_ULL(arr[i]); + } + + if (bitmap_weight(&w, sz) != sz) { + dev_err(rvu->dev, + "Duplicate or out-of-range subbank index. %lu\n", + find_first_zero_bit(&w, sz)); + return -EINVAL; + } + + return 0; +} + static const struct devlink_ops rvu_devlink_ops = { .eswitch_mode_get = rvu_devlink_eswitch_mode_get, .eswitch_mode_set = rvu_devlink_eswitch_mode_set, }; -static const struct devlink_param rvu_af_dl_param_defrag[] = { +static const struct devlink_param rvu_af_dl_cn20k_params[] = { + DEVLINK_PARAM_DRIVER(RVU_AF_DEVLINK_PARAM_ID_NPC_SRCH_ORDER, + "npc_srch_order", DEVLINK_PARAM_TYPE_U32_ARRAY, + BIT(DEVLINK_PARAM_CMODE_RUNTIME), + rvu_af_dl_npc_srch_order_get, + rvu_af_dl_npc_srch_order_set, + rvu_af_dl_npc_srch_order_validate), DEVLINK_PARAM_DRIVER(RVU_AF_DEVLINK_PARAM_ID_NPC_DEFRAG, "npc_defrag", DEVLINK_PARAM_TYPE_STRING, BIT(DEVLINK_PARAM_CMODE_RUNTIME), @@ -1666,13 +1738,13 @@ int rvu_register_dl(struct rvu *rvu) } if (is_cn20k(rvu->pdev)) { - err = devlink_params_register(dl, rvu_af_dl_param_defrag, - ARRAY_SIZE(rvu_af_dl_param_defrag)); + err = devlink_params_register(dl, rvu_af_dl_cn20k_params, + ARRAY_SIZE(rvu_af_dl_cn20k_params)); if (err) { dev_err(rvu->dev, - "devlink defrag params register failed with error %d", + "devlink cn20k params register failed with error %d", err); - goto err_dl_defrag; + goto err_dl_cn20k_params; } } @@ -1695,10 +1767,10 @@ int rvu_register_dl(struct rvu *rvu) err_dl_exact_match: if (is_cn20k(rvu->pdev)) - devlink_params_unregister(dl, rvu_af_dl_param_defrag, - ARRAY_SIZE(rvu_af_dl_param_defrag)); + devlink_params_unregister(dl, rvu_af_dl_cn20k_params, + ARRAY_SIZE(rvu_af_dl_cn20k_params)); -err_dl_defrag: +err_dl_cn20k_params: devlink_params_unregister(dl, rvu_af_dl_params, ARRAY_SIZE(rvu_af_dl_params)); err_dl_health: @@ -1717,8 +1789,8 @@ void rvu_unregister_dl(struct rvu *rvu) devlink_params_unregister(dl, rvu_af_dl_params, ARRAY_SIZE(rvu_af_dl_params)); if (is_cn20k(rvu->pdev)) - devlink_params_unregister(dl, rvu_af_dl_param_defrag, - ARRAY_SIZE(rvu_af_dl_param_defrag)); + devlink_params_unregister(dl, rvu_af_dl_cn20k_params, + ARRAY_SIZE(rvu_af_dl_cn20k_params)); /* Unregister exact match devlink only for CN10K-B */ if (rvu_npc_exact_has_match_table(rvu)) -- 2.43.0