From: Lad Prabhakar Add support for an optional "ts" (timestamp) clock to the RZN1 A5PSW driver. Some SoC variants provide a dedicated clock source for timestamping or time synchronization features within the Ethernet switch IP. Request and enable this clock during probe if defined in the device tree. If the clock is not present, the driver continues to operate normally. This change prepares the driver for Renesas RZ/T2H and RZ/N2H SoCs, where the Ethernet switch includes a timestamp clock input. Signed-off-by: Lad Prabhakar --- drivers/net/dsa/rzn1_a5psw.c | 7 +++++++ drivers/net/dsa/rzn1_a5psw.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/drivers/net/dsa/rzn1_a5psw.c b/drivers/net/dsa/rzn1_a5psw.c index 7b84585a5415..99098bc06efe 100644 --- a/drivers/net/dsa/rzn1_a5psw.c +++ b/drivers/net/dsa/rzn1_a5psw.c @@ -1243,6 +1243,13 @@ static int a5psw_probe(struct platform_device *pdev) goto free_pcs; } + a5psw->ts = devm_clk_get_optional_enabled(dev, "ts"); + if (IS_ERR(a5psw->ts)) { + dev_err(dev, "failed get ts clock\n"); + ret = PTR_ERR(a5psw->ts); + goto free_pcs; + } + reset = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL); if (IS_ERR(reset)) { ret = PTR_ERR(reset); diff --git a/drivers/net/dsa/rzn1_a5psw.h b/drivers/net/dsa/rzn1_a5psw.h index d54acedac194..81be30d6c55f 100644 --- a/drivers/net/dsa/rzn1_a5psw.h +++ b/drivers/net/dsa/rzn1_a5psw.h @@ -236,6 +236,7 @@ union lk_data { * @base: Base address of the switch * @hclk: hclk_switch clock * @clk: clk_switch clock + * @ts: Timestamp clock * @dev: Device associated to the switch * @mii_bus: MDIO bus struct * @mdio_freq: MDIO bus frequency requested @@ -251,6 +252,7 @@ struct a5psw { void __iomem *base; struct clk *hclk; struct clk *clk; + struct clk *ts; struct device *dev; struct mii_bus *mii_bus; struct phylink_pcs *pcs[A5PSW_PORTS_NUM - 1]; -- 2.52.0