Now that perf operates on a KVM-provided snapshot of PMU state, handled cross-mapped PEBS counters entirely in KVM by clearing unusable counters from the to-be-enabled mask instead of foisting the work on perf. No functional change intended. Reviewed-by: Dapeng Mi Signed-off-by: Sean Christopherson --- arch/x86/events/intel/core.c | 8 -------- arch/x86/include/asm/perf_event.h | 1 - arch/x86/kvm/vmx/vmx.c | 10 ++++++++-- 3 files changed, 8 insertions(+), 11 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 66cacfeb47d3..d9315bb2f221 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5379,14 +5379,6 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, ~cpuc->intel_ctrl_exclude_guest_mask & cpuc->intel_ctrl_exclude_host_mask; - /* - * Disable counters where the guest PMC is different than the host PMC - * being used on behalf of the guest, as the PEBS record includes - * PERF_GLOBAL_STATUS, i.e. the guest will see overflow status for the - * wrong counter(s). - */ - guest_pebs_mask &= ~guest_pebs->cross_mapped_mask; - /* * FIXME: Allow guest and host usage of PEBS events to co-exist instead * of disabling guest PEBS entirely if the host is using PEBS. diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 27f9c5bee7b0..5c92d43bbef8 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -823,7 +823,6 @@ struct x86_guest_pebs { u64 enable; u64 ds_area; u64 data_cfg; - u64 cross_mapped_mask; }; #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL) extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index b097db296792..8f7d0620f44c 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7369,8 +7369,14 @@ static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) .data_cfg = pmu->pebs_data_cfg, }; - if (pmu->pebs_enable & pmu->global_ctrl) - guest_pebs.cross_mapped_mask = intel_pmu_get_cross_mapped_mask(pmu); + /* + * Disable counters where the guest PMC is different than the host PMC + * being used on behalf of the guest, as the PEBS record includes + * PERF_GLOBAL_STATUS, i.e. the guest will see overflow status for the + * wrong counter(s). + */ + if (guest_pebs.enable & pmu->global_ctrl) + guest_pebs.enable &= ~intel_pmu_get_cross_mapped_mask(pmu); /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */ msrs = perf_guest_get_msrs(&nr_msrs, &guest_pebs); -- 2.55.0.1082.g2b9226bbc0-goog