The event stream control bits are the same for both CNTHCTL and CNTKCTL so rather than duplicating the definitions rename them to be useful in both cases. We will need these in a later commit when we start implementing event streams. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée --- target/arm/internals.h | 11 +++++++---- target/arm/helper.c | 8 ++++---- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 85980f0e69a..dc593f1fec8 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -263,14 +263,17 @@ FIELD(VSTCR, SA, 30, 1) * have different bit definitions, and EL1PCTEN might be * bit 0 or bit 10. We use _E2H1 and _E2H0 suffixes to * disambiguate if necessary. + * + * The event stream bits (EVN*) are in the same position for + * CNTKCTL_EL1/CTNKCTL. */ FIELD(CNTHCTL, EL0PCTEN_E2H1, 0, 1) FIELD(CNTHCTL, EL0VCTEN_E2H1, 1, 1) FIELD(CNTHCTL, EL1PCTEN_E2H0, 0, 1) FIELD(CNTHCTL, EL1PCEN_E2H0, 1, 1) -FIELD(CNTHCTL, EVNTEN, 2, 1) -FIELD(CNTHCTL, EVNTDIR, 3, 1) -FIELD(CNTHCTL, EVNTI, 4, 4) +FIELD(CNTxCTL, EVNTEN, 2, 1) +FIELD(CNTxCTL, EVNTDIR, 3, 1) +FIELD(CNTxCTL, EVNTI, 4, 4) FIELD(CNTHCTL, EL0VTEN, 8, 1) FIELD(CNTHCTL, EL0PTEN, 9, 1) FIELD(CNTHCTL, EL1PCTEN_E2H1, 10, 1) @@ -280,7 +283,7 @@ FIELD(CNTHCTL, EL1TVT, 13, 1) FIELD(CNTHCTL, EL1TVCT, 14, 1) FIELD(CNTHCTL, EL1NVPCT, 15, 1) FIELD(CNTHCTL, EL1NVVCT, 16, 1) -FIELD(CNTHCTL, EVNTIS, 17, 1) +FIELD(CNTxCTL, EVNTIS, 17, 1) FIELD(CNTHCTL, CNTVMASK, 18, 1) FIELD(CNTHCTL, CNTPMASK, 19, 1) diff --git a/target/arm/helper.c b/target/arm/helper.c index 40dd070d2c1..81a07ca42d0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1746,9 +1746,9 @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri, uint32_t valid_mask = R_CNTHCTL_EL0PCTEN_E2H1_MASK | R_CNTHCTL_EL0VCTEN_E2H1_MASK | - R_CNTHCTL_EVNTEN_MASK | - R_CNTHCTL_EVNTDIR_MASK | - R_CNTHCTL_EVNTI_MASK | + R_CNTxCTL_EVNTEN_MASK | + R_CNTxCTL_EVNTDIR_MASK | + R_CNTxCTL_EVNTI_MASK | R_CNTHCTL_EL0VTEN_MASK | R_CNTHCTL_EL0PTEN_MASK | R_CNTHCTL_EL1PCTEN_E2H1_MASK | @@ -1763,7 +1763,7 @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri, R_CNTHCTL_EL1TVCT_MASK | R_CNTHCTL_EL1NVPCT_MASK | R_CNTHCTL_EL1NVVCT_MASK | - R_CNTHCTL_EVNTIS_MASK; + R_CNTxCTL_EVNTIS_MASK; } if (cpu_isar_feature(aa64_ecv, cpu)) { valid_mask |= R_CNTHCTL_ECV_MASK; -- 2.47.3