dm_crtc_get_scanoutpos() packs decoded DC positions and blanking boundaries into u32 words, shifting the second value by 16 bits. VRR extends vertical blanking without changing the line clock. For example, a 4K240 mode with vtotal=2250 spans about 9000 lines per refresh at 60 Hz, exceeding the 13 bit range within a 48-240 Hz VRR range. The 13 bit mask truncates positions above 8191, causing early VRR timestamps and missed vblank count adjustments. Fixes: e806208dc1da ("drm/amd/display: Fix slow FPS.") Cc: stable@vger.kernel.org Signed-off-by: Erhan Bilgili --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 0a8dd7241750..f78c82ba7f70 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1767,6 +1767,8 @@ int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, bool in_vbl = true; struct amdgpu_device *adev = drm_to_adev(dev); + /* DC packs decoded values into 16 bit fields. */ + const u32 scanout_mask = adev->dc_enabled ? 0xffff : 0x1fff; /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ @@ -1784,15 +1786,15 @@ int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ /* Decode into vertical and horizontal scanout position. */ - *vpos = position & 0x1fff; - *hpos = (position >> 16) & 0x1fff; + *vpos = position & scanout_mask; + *hpos = (position >> 16) & scanout_mask; /* Valid vblank area boundaries from gpu retrieved? */ if (vbl > 0) { /* Yes: Decode. */ ret |= DRM_SCANOUTPOS_ACCURATE; - vbl_start = vbl & 0x1fff; - vbl_end = (vbl >> 16) & 0x1fff; + vbl_start = vbl & scanout_mask; + vbl_end = (vbl >> 16) & scanout_mask; } else { /* No: Fake something reasonable which gives at least ok results. */ vbl_start = mode->crtc_vdisplay; -- 2.56.0