Extend the existing RTL8367S SGMII/HSGMII PCS implementation in this driver for family D switches, whose CPU SerDes is reached through the indexed SDS13 window and whose SDS_MISC fields differ from family C. The register sequence and tuning tables are derived from the GPL-licensed Realtek RTL8367D port API distributed in the Mercusys MR80X GPL release. Keep the existing family C path unchanged and select the new behavior from the driver's chip-family metadata, making the implementation reusable by other family D boards. This patch only prepares the family D paths; they become reachable when the RTL8367S-VB chip entry is added in the last patch. Co-developed-by: Fabiano Tassotti Signed-off-by: Fabiano Tassotti Signed-off-by: Mieczyslaw Nalewaj --- drivers/net/dsa/realtek/rtl8365mb_main.c | 226 +++++++++++++++++------ 1 file changed, 173 insertions(+), 53 deletions(-) diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c index f31d72a..d23e80f 100644 --- a/drivers/net/dsa/realtek/rtl8365mb_main.c +++ b/drivers/net/dsa/realtek/rtl8365mb_main.c @@ -262,7 +262,8 @@ * interface, indexed by the external port number with port 5 (the first * external port) as the base. Other RTL8367 families index this register * differently (e.g. the RTL8367R uses (id + 1) % 2), so this mapping only - * holds for the RTL8367C-style parts this driver supports. + * holds for the RTL8367C-style parts and for family D, where it is the same + * (one bit per external port, base port 5), as in the vendor RTL8367D API. */ #define RTL8365MB_BYPASS_LINE_RATE_REG 0x03F7 #define RTL8365MB_BYPASS_LINE_RATE_MASK(_port) BIT((_port) - 5) @@ -284,6 +285,7 @@ #define RTL8365MB_SDS_INDACS_CMD_BUSY_MASK BIT(8) #define RTL8365MB_SDS_INDACS_CMD_RUN_MASK BIT(7) #define RTL8365MB_SDS_INDACS_CMD_WR_MASK BIT(6) +#define RTL8365MB_SDS_INDACS_CMD_INDEX_MASK GENMASK(5, 0) #define RTL8365MB_SDS_INDACS_ADR_REG 0x6601 #define RTL8365MB_SDS_INDACS_DATA_REG 0x6602 @@ -313,8 +315,10 @@ #define RTL8365MB_SDS_REG_LINK_STATUS 0x003d #define RTL8365MB_SDS_LINK_STATUS_LINK_MASK BIT(4) -/* The embedded SerDes can only be muxed to external interface 1 (MAC8), - * which is port 6. +/* On family C the embedded SerDes can only be muxed to external interface + * 1 (MAC8), which is port 6. Family D has it on external interface 0 + * (MAC6), see RTL8365MB_D_SDS_EXT0_INDEX. RTL8365MB_SDS_EXT_INTERFACE_ID + * below is the family C id; the SerDes port is 6 on both families. */ #define RTL8365MB_SDS_EXT_INTERFACE_ID 1 #define RTL8365MB_SDS_EXT_INTERFACE_PORT 6 @@ -332,7 +336,22 @@ #define RTL8365MB_SDS_OPTION_ARM_KEY 0x0249 #define RTL8365MB_SDS_OPTION_REG 0x13C1 +/* Family D uses the SDS13 indirect window for its MAC6 SerDes. */ +#define RTL8365MB_D_SDS_EXT0_INDEX 13 +#define RTL8365MB_D_FIBER_CFG2_REG 0x13E8 +#define RTL8365MB_D_FIBER_CFG2_RX_DISABLE_MASK GENMASK(7, 6) +#define RTL8365MB_D_FIBER_CFG2_RX_DISABLE_SDS0 BIT(6) +#define RTL8365MB_D_SDS_MISC_PA33PC_EN BIT(11) +#define RTL8365MB_D_SDS_MISC_PA12PC_EN BIT(10) +#define RTL8365MB_D_SDS_MISC_MAC6_SEL_SDS0 BIT(9) #define RTL8365MB_D_SDS_MISC_MODE_FIELD_MASK GENMASK(4, 0) +#define RTL8365MB_D_SDS_MISC_MODE_SGMII 0x02 +#define RTL8365MB_D_SDS_MISC_MODE_HSGMII 0x12 +#define RTL8365MB_D_SDS_MISC_CFG_MASK \ + (RTL8365MB_D_SDS_MISC_PA33PC_EN | \ + RTL8365MB_D_SDS_MISC_PA12PC_EN | \ + RTL8365MB_D_SDS_MISC_MAC6_SEL_SDS0 | \ + RTL8365MB_D_SDS_MISC_MODE_FIELD_MASK) /* Shared "disable" encoding for both SDS_MISC's and SDS1_MISC0's * 5-bit mode fields. */ @@ -720,6 +739,21 @@ static const struct rtl8365mb_jam_tbl_entry rtl8365mb_sds_jam_hsgmii[] = { { 0x0424, 0xD810 }, { 0x0001, 0x0F80 }, { 0x002E, 0x83F2 }, }; +/* Family D tuning tables from the Realtek vendor port API. */ +static const struct rtl8365mb_jam_tbl_entry rtl8365mb_d_sds_jam_sgmii[] = { + { 0x0427, 0x4E0C }, { 0x0428, 0xAA00 }, { 0x0425, 0x5189 }, + { 0x0424, 0x8414 }, { 0x0423, 0x1020 }, { 0x0410, 0x0002 }, + { 0x0484, 0x011B }, { 0x0421, 0x8E13 }, { 0x0422, 0x1140 }, + { 0x0004, 0x074F }, +}; + +static const struct rtl8365mb_jam_tbl_entry rtl8365mb_d_sds_jam_hsgmii[] = { + { 0x0427, 0x4E0C }, { 0x0428, 0xAA00 }, { 0x0425, 0x5189 }, + { 0x0424, 0x8414 }, { 0x0423, 0x1020 }, { 0x0410, 0x0002 }, + { 0x0504, 0x051B }, { 0x0421, 0x8E13 }, { 0x0422, 0x1140 }, + { 0x0004, 0x074F }, +}; + enum rtl8365mb_phy_interface_mode { RTL8365MB_PHY_INTERFACE_MODE_INVAL = 0, RTL8365MB_PHY_INTERFACE_MODE_INTERNAL = BIT(0), @@ -1323,7 +1357,8 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, return 0; } -static int rtl8365mb_sds_write(struct realtek_priv *priv, u16 addr, u16 data) +static int rtl8365mb_sds_write(struct realtek_priv *priv, u8 index, + u16 addr, u16 data) { int ret; @@ -1341,10 +1376,13 @@ static int rtl8365mb_sds_write(struct realtek_priv *priv, u16 addr, u16 data) */ return regmap_write(priv->map, RTL8365MB_SDS_INDACS_CMD_REG, RTL8365MB_SDS_INDACS_CMD_RUN_MASK | - RTL8365MB_SDS_INDACS_CMD_WR_MASK); + RTL8365MB_SDS_INDACS_CMD_WR_MASK | + FIELD_PREP(RTL8365MB_SDS_INDACS_CMD_INDEX_MASK, + index)); } -static int rtl8365mb_sds_read(struct realtek_priv *priv, u16 addr, u16 *data) +static int rtl8365mb_sds_read(struct realtek_priv *priv, u8 index, + u16 addr, u16 *data) { u32 val; int ret; @@ -1354,7 +1392,9 @@ static int rtl8365mb_sds_read(struct realtek_priv *priv, u16 addr, u16 *data) return ret; ret = regmap_write(priv->map, RTL8365MB_SDS_INDACS_CMD_REG, - RTL8365MB_SDS_INDACS_CMD_RUN_MASK); + RTL8365MB_SDS_INDACS_CMD_RUN_MASK | + FIELD_PREP(RTL8365MB_SDS_INDACS_CMD_INDEX_MASK, + index)); if (ret) return ret; @@ -1394,6 +1434,14 @@ static int rtl8365mb_sds_probe_option(struct realtek_priv *priv) int ret; int i; + /* Family D has a fixed SDS13 programming model and does not use the + * family C option register to select its tuning table. + */ + if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D) { + mb->sds_supported = true; + return 0; + } + /* Nothing to probe if no external interface is wired to the SerDes */ for (i = 0; i < RTL8365MB_MAX_NUM_EXTINTS; i++) { extint = &mb->chip_info->extints[i]; @@ -1472,28 +1520,47 @@ static int rtl8365mb_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, const unsigned long *advertising, bool permit_pause_to_mac) { - const struct rtl8365mb_jam_tbl_entry *sds_jam; const int id = RTL8365MB_SDS_EXT_INTERFACE_ID; + const struct rtl8365mb_jam_tbl_entry *sds_jam; struct rtl8365mb *mb = pcs_to_rtl8365mb(pcs); - struct realtek_priv *priv; + struct realtek_priv *priv = mb->priv; size_t sds_jam_size; - u32 mode; + u32 misc_mask; + u32 misc_val; + u32 sds_mode; + u8 sds_index; + bool is_d; u16 val; int ret; int i; - priv = mb->priv; + is_d = rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D; + /* Select the appropriate tuning table and SDS mode */ if (interface == PHY_INTERFACE_MODE_2500BASEX) { - sds_jam = rtl8365mb_sds_jam_hsgmii; - sds_jam_size = ARRAY_SIZE(rtl8365mb_sds_jam_hsgmii); - mode = RTL8365MB_EXT_PORT_MODE_HSGMII; + if (is_d) { + sds_jam = rtl8365mb_d_sds_jam_hsgmii; + sds_jam_size = ARRAY_SIZE(rtl8365mb_d_sds_jam_hsgmii); + sds_mode = RTL8365MB_D_SDS_MISC_MODE_HSGMII; + } else { + sds_jam = rtl8365mb_sds_jam_hsgmii; + sds_jam_size = ARRAY_SIZE(rtl8365mb_sds_jam_hsgmii); + sds_mode = RTL8365MB_EXT_PORT_MODE_HSGMII; + } } else { - sds_jam = rtl8365mb_sds_jam_sgmii; - sds_jam_size = ARRAY_SIZE(rtl8365mb_sds_jam_sgmii); - mode = RTL8365MB_EXT_PORT_MODE_SGMII; + if (is_d) { + sds_jam = rtl8365mb_d_sds_jam_sgmii; + sds_jam_size = ARRAY_SIZE(rtl8365mb_d_sds_jam_sgmii); + sds_mode = RTL8365MB_D_SDS_MISC_MODE_SGMII; + } else { + sds_jam = rtl8365mb_sds_jam_sgmii; + sds_jam_size = ARRAY_SIZE(rtl8365mb_sds_jam_sgmii); + sds_mode = RTL8365MB_EXT_PORT_MODE_SGMII; + } } + sds_index = is_d ? RTL8365MB_D_SDS_EXT0_INDEX : 0; + /* Hold the embedded DW8051 microcontroller in reset and keep it * disabled. The vendor driver loads firmware into it to manage the * SerDes link, but the firmware only duplicates work that phylink @@ -1522,34 +1589,53 @@ static int rtl8365mb_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, /* Tune the SerDes with vendor-prescribed parameters */ for (i = 0; i < sds_jam_size; i++) { - ret = rtl8365mb_sds_write(priv, sds_jam[i].reg, - sds_jam[i].val); + ret = rtl8365mb_sds_write(priv, sds_index, + sds_jam[i].reg, sds_jam[i].val); + if (ret) + return ret; + } + + /* Family-specific post-tuning configuration */ + if (is_d) { + ret = regmap_update_bits(priv->map, RTL8365MB_D_FIBER_CFG2_REG, + RTL8365MB_D_FIBER_CFG2_RX_DISABLE_MASK, + RTL8365MB_D_FIBER_CFG2_RX_DISABLE_SDS0); if (ret) return ret; + + misc_mask = RTL8365MB_D_SDS_MISC_CFG_MASK; + misc_val = RTL8365MB_D_SDS_MISC_PA33PC_EN | + RTL8365MB_D_SDS_MISC_PA12PC_EN | + RTL8365MB_D_SDS_MISC_MAC6_SEL_SDS0 | sds_mode; + } else { + /* Mux the SerDes to MAC8 in the requested mode */ + misc_mask = RTL8365MB_SDS_MISC_MAC8_SEL_SGMII_MASK | + RTL8365MB_SDS_MISC_MAC8_SEL_HSGMII_MASK; + misc_val = (sds_mode == RTL8365MB_EXT_PORT_MODE_SGMII) ? + RTL8365MB_SDS_MISC_MAC8_SEL_SGMII_MASK : + RTL8365MB_SDS_MISC_MAC8_SEL_HSGMII_MASK; } - /* Mux the SerDes to MAC8 in the requested mode */ ret = regmap_update_bits(priv->map, RTL8365MB_SDS_MISC_REG, - RTL8365MB_SDS_MISC_MAC8_SEL_SGMII_MASK | - RTL8365MB_SDS_MISC_MAC8_SEL_HSGMII_MASK, - mode == RTL8365MB_EXT_PORT_MODE_SGMII ? - RTL8365MB_SDS_MISC_MAC8_SEL_SGMII_MASK : - RTL8365MB_SDS_MISC_MAC8_SEL_HSGMII_MASK); + misc_mask, misc_val); if (ret) return ret; - val = mode << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(id); - ret = regmap_update_bits(priv->map, - RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(id), - RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(id), - val); - if (ret) - return ret; + if (!is_d) { + val = sds_mode << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(id); + ret = regmap_update_bits(priv->map, + RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(id), + RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(id), + val); + if (ret) + return ret; + } /* Take the SerDes out of reset. The vendor driver does this only * after the SerDes mux and the interface mode are configured. */ - ret = rtl8365mb_sds_write(priv, RTL8365MB_SDS_REG_RESET, + ret = rtl8365mb_sds_write(priv, sds_index, + RTL8365MB_SDS_REG_RESET, RTL8365MB_SDS_RESET_DEASSERT); if (ret) return ret; @@ -1559,27 +1645,32 @@ static int rtl8365mb_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, * This flushes the FIFOs and ensures a clean state for the link, * preventing silent drops and CRC errors. */ - ret = rtl8365mb_sds_write(priv, RTL8365MB_SDS_REG_BMCR, + ret = rtl8365mb_sds_write(priv, sds_index, + RTL8365MB_SDS_REG_BMCR, RTL8365MB_SDS_BMCR_DPRST_PHASE1); if (ret) return ret; - ret = rtl8365mb_sds_write(priv, RTL8365MB_SDS_REG_BMCR, + ret = rtl8365mb_sds_write(priv, sds_index, + RTL8365MB_SDS_REG_BMCR, RTL8365MB_SDS_BMCR_DPRST_PHASE2); if (ret) return ret; /* Keep SGMII in-band autonegotiation disabled: the link parameters are - * forced from rtl8365mb_pcs_link_up() instead. + * forced from rtl8365mb_pcs_link_up() instead (family C), or from + * mac_link_up() (family D). */ - ret = rtl8365mb_sds_read(priv, RTL8365MB_SDS_REG_NWAY, &val); + ret = rtl8365mb_sds_read(priv, sds_index, + RTL8365MB_SDS_REG_NWAY, &val); if (ret) return ret; val &= ~RTL8365MB_SDS_NWAY_EN_MASK; val |= RTL8365MB_SDS_NWAY_RESTART_MASK; - return rtl8365mb_sds_write(priv, RTL8365MB_SDS_REG_NWAY, val); + return rtl8365mb_sds_write(priv, sds_index, + RTL8365MB_SDS_REG_NWAY, val); } static bool rtl8365mb_interface_is_serdes(phy_interface_t interface) @@ -1604,18 +1695,27 @@ static void rtl8365mb_pcs_get_state(struct phylink_pcs *pcs, { struct rtl8365mb *mb = pcs_to_rtl8365mb(pcs); struct realtek_priv *priv = mb->priv; + u8 sds_index = 0; u16 status; + bool is_d; u32 val; int ret; - /* In-band autonegotiation is not implemented, so the link parameters are - * forced from rtl8365mb_pcs_link_up(). The real link state must still be - * read from the SerDes itself: the embedded DW8051 microcontroller that + is_d = rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D; + + /* In-band autonegotiation is not implemented, so the link parameters + * are forced from rtl8365mb_pcs_link_up() on family C, and from + * mac_link_up() on family D. The real link state must still be read + * from the SerDes itself: the embedded DW8051 microcontroller that * the vendor firmware uses to poll the SerDes is kept disabled (see * rtl8365mb_pcs_config()), so the link status register can be read * directly through the SDS_INDACS window without racing the auto-poll. */ - ret = rtl8365mb_sds_read(priv, RTL8365MB_SDS_REG_LINK_STATUS, &status); + if (is_d) + sds_index = RTL8365MB_D_SDS_EXT0_INDEX; + + ret = rtl8365mb_sds_read(priv, sds_index, + RTL8365MB_SDS_REG_LINK_STATUS, &status); if (ret) { state->link = false; return; @@ -1626,6 +1726,17 @@ static void rtl8365mb_pcs_get_state(struct phylink_pcs *pcs, if (!state->link) return; + if (is_d) { + /* Only 2500base-x is a fixed rate; for the other modes keep + * the speed and duplex phylink passed in. + */ + if (state->interface == PHY_INTERFACE_MODE_2500BASEX) { + state->duplex = DUPLEX_FULL; + state->speed = SPEED_2500; + } + return; + } + /* The speed and duplex are forced; read them back from the values * programmed into the SerDes MISC register. */ @@ -1667,6 +1778,12 @@ static void rtl8365mb_pcs_link_up(struct phylink_pcs *pcs, u32 r_speed; int ret; + /* Family D forces the external MAC ability from mac_link_up(); its + * SDS_MISC fields do not share the family C link-force layout. + */ + if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D) + return; + /* The speed field has no value for 2.5 Gbps: the rate is determined by * the HSGMII SerDes configuration, and the vendor driver programs the * 1 Gbps value here. @@ -1985,18 +2102,21 @@ static void rtl8365mb_phylink_mac_link_up(struct phylink_config *config, return; } - /* The SerDes has its own pause enables; program them from - * the resolved pause modes, as the vendor driver does when - * forcing the link on a SerDes external interface. These - * bits, not the MAC force pause bits, gate pause on the - * SerDes external interface: flow control testing shows - * that pause frames are only emitted with the SerDes TXFC - * bit set, while the MAC force pause bits alone have no - * effect on this port. This is done here rather than in - * rtl8365mb_pcs_link_up() because pcs_link_up() carries no - * pause information. + /* Family C: the SerDes has its own pause enables; program + * them from the resolved pause modes, as the vendor driver + * does when forcing the link on a SerDes external + * interface. These bits, not the MAC force pause bits, gate + * pause on the SerDes external interface: flow control + * testing shows that pause frames are only emitted with the + * SerDes TXFC bit set, while the MAC force pause bits alone + * have no effect on this port. This is done here rather + * than in rtl8365mb_pcs_link_up() because pcs_link_up() + * carries no pause information. Family D does not use this + * path: its pause bits are set in the forced-mode register + * by rtl8365mb_ext_config_forcemode(). */ - if (rtl8365mb_interface_is_serdes(interface)) { + if (rtl8365mb_interface_is_serdes(interface) && + rtl8365mb_get_family(priv) != RTL8365MB_FAMILY_D) { u32 val = 0; if (tx_pause) -- 2.53.0