From: Saswati Das Add the Hardware-Software Interface (HSI) structure and macro definitions required to support 64-bit doorbells and Multi-Path Channel (MPC) firmware commands/completions for next-generation RoCE: - Add struct dbc_dbc64: Introduce the 64-bit doorbell layout along with field masks, shift offsets, and type/path enumerations. This includes queue types (SQ, RQ, SRQ, CQ, NQ, etc.) and paths (ROCE, L2, ENGINE). - Add MPC Command Macros: Define the main MPC request types (ICA, RCA, PFVF, EVENT) and their corresponding subtypes used to manage security associations (SA enable, key rotation, SA stats/init), QP/AH modification/batching, and PF/VF commands (QP/AH creation, modification, and destruction). - Add MPC Completion Macros & Structs: Add completion error codes for ICA and introduce the 8-byte completion header structure (struct mpc_cmpl_hdr) used to parse MPC firmware responses. These definitions will be used by the driver to interface with the firmware over the MPC/PRIMATE channels. Signed-off-by: Saswati Das Signed-off-by: Siva Reddy Kallam Reviewed-by: Vikas Gupta Reviewed-by: Dharmender Garg --- include/linux/bnge/hsi.h | 161 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 161 insertions(+) diff --git a/include/linux/bnge/hsi.h b/include/linux/bnge/hsi.h index 1f7bd96415a5..a3383f2c7381 100644 --- a/include/linux/bnge/hsi.h +++ b/include/linux/bnge/hsi.h @@ -12510,6 +12510,43 @@ struct dbc_dbc { #define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL }; +/* dbc_dbc64 (size:64b/8B) */ +struct dbc_dbc64 { + __le64 dbc; + #define DBC_DBC64_INDEX_MASK 0xffffffUL + #define DBC_DBC64_INDEX_SFT 0 + #define DBC_DBC64_EPOCH 0x1000000UL + #define DBC_DBC64_TOGGLE_MASK 0x6000000UL + #define DBC_DBC64_TOGGLE_SFT 25 + #define DBC_DBC64_XID_MASK 0xfffff00000000ULL + #define DBC_DBC64_XID_SFT 32 + #define DBC_DBC64_PATH_MASK 0x300000000000000ULL + #define DBC_DBC64_PATH_SFT 56 + #define DBC_DBC64_PATH_ROCE (0x0ULL << 56) + #define DBC_DBC64_PATH_L2 (0x1ULL << 56) + #define DBC_DBC64_PATH_ENGINE (0x2ULL << 56) + #define DBC_DBC64_PATH_LAST DBC_DBC64_PATH_ENGINE + #define DBC_DBC64_VALID 0x400000000000000ULL + #define DBC_DBC64_DEBUG_TRACE 0x800000000000000ULL + #define DBC_DBC64_TYPE_MASK 0xf000000000000000ULL + #define DBC_DBC64_TYPE_SFT 60 + #define DBC_DBC64_TYPE_SQ (0x0ULL << 60) + #define DBC_DBC64_TYPE_RQ (0x1ULL << 60) + #define DBC_DBC64_TYPE_SRQ (0x2ULL << 60) + #define DBC_DBC64_TYPE_SRQ_ARM (0x3ULL << 60) + #define DBC_DBC64_TYPE_CQ (0x4ULL << 60) + #define DBC_DBC64_TYPE_CQ_ARMSE (0x5ULL << 60) + #define DBC_DBC64_TYPE_CQ_ARMALL (0x6ULL << 60) + #define DBC_DBC64_TYPE_CQ_ARMENA (0x7ULL << 60) + #define DBC_DBC64_TYPE_SRQ_ARMENA (0x8ULL << 60) + #define DBC_DBC64_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60) + #define DBC_DBC64_TYPE_NQ (0xaULL << 60) + #define DBC_DBC64_TYPE_NQ_ARM (0xbULL << 60) + #define DBC_DBC64_TYPE_NQ_MASK (0xeULL << 60) + #define DBC_DBC64_TYPE_NULL (0xfULL << 60) + #define DBC_DBC64_TYPE_LAST DBC_DBC64_TYPE_NULL +}; + /* db_push_start (size:64b/8B) */ struct db_push_start { u64 db; @@ -12605,4 +12642,128 @@ struct hcomm_status { #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL +/* MPC macros */ +#define MPC_CMD_HDR_REQ_TYPE_ICA 0x1UL +#define MPC_CMD_HDR_REQ_TYPE_RCA 0x2UL +#define MPC_CMD_HDR_REQ_TYPE_PFVF 0x3UL +#define MPC_CMD_HDR_REQ_TYPE_EVENT 0x4UL +#define MPC_CMD_HDR_REQ_TYPE_LAST MPC_CMD_HDR_REQ_TYPE_EVENT + +#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SA_ENABLE 0x0UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SM_PSP_SA_INIT 0x1UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SM_PSP_NEW_RX_ASSOC 0x2UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SM_PSP_KEY_ROTATE 0x3UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_CM_PSP_SA_INIT 0x4UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_CM_PSP_KEY_ROTATE 0x5UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_CM_PSP_KEY_SET 0x6UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SA_INFO_GET 0x7UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SA_STATS_GET 0x8UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SA_STATS_CLEAR 0x9UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SA_RX_MATCH_RULE_SET 0xaUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SM_PSP_SA_SET 0xbUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_QP_MODIFY 0x0UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_AH_MODIFY 0x1UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_QP_MODIFY_CMPL 0x2UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_AH_MODIFY_CMPL 0x3UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_QP_MODIFY_BATCH 0x4UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_AH_MODIFY_BATCH 0x5UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_QP_MODIFY_BATCH_CMPL 0x6UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_AH_MODIFY_BATCH_CMPL 0x7UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_MPC_TEST_CMD 0xc8UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_MPC_TEST_CMPL 0xc9UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_EVENT_RESP_CMPL 0x0UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_CREATE 0x0UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_CREATE 0x1UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_MODIFY 0x2UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_MODIFY 0x3UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_DESTROY 0x4UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_DESTROY 0x5UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_CREATE_CMPL 0xaUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_CREATE_CMPL 0xbUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_MODIFY_CMPL 0xcUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_MODIFY_CMPL 0xdUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_DESTROY_CMPL 0xeUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_DESTROY_CMPL 0xfUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_CREATE_FWD_REQ 0x14UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_CREATE_FWD_REQ 0x15UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_MODIFY_FWD_REQ 0x16UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_MODIFY_FWD_REQ 0x17UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_DESTROY_FWD_REQ 0x18UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_DESTROY_FWD_REQ 0x19UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_CREATE_FWD_RESP 0x1eUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_CREATE_FWD_RESP 0x1fUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_MODIFY_FWD_RESP 0x20UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_MODIFY_FWD_RESP 0x21UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_DESTROY_FWD_RESP 0x22UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_DESTROY_FWD_RESP 0x23UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_ALL_FWD_RESP_CMPL 0x28UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_CREATE_BATCH 0x32UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_CREATE_BATCH 0x33UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_MODIFY_BATCH 0x34UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_MODIFY_BATCH 0x35UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_DESTROY_BATCH 0x36UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_DESTROY_BATCH 0x37UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_CREATE_BATCH_CMPL 0x3cUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_CREATE_BATCH_CMPL 0x3dUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_MODIFY_BATCH_CMPL 0x3eUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_MODIFY_BATCH_CMPL 0x3fUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_DESTROY_BATCH_CMPL 0x40UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_DESTROY_BATCH_CMPL 0x41UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_CREATE_BATCH_FWD_REQ 0x46UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_CREATE_BATCH_FWD_REQ 0x47UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_MODIFY_BATCH_FWD_REQ 0x48UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_MODIFY_BATCH_FWD_REQ 0x49UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_DESTROY_BATCH_FWD_REQ 0x4aUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_DESTROY_BATCH_FWD_REQ 0x4bUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_CREATE_BATCH_FWD_RESP 0x50UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_CREATE_BATCH_FWD_RESP 0x51UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_MODIFY_BATCH_FWD_RESP 0x52UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_MODIFY_BATCH_FWD_RESP 0x53UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_DESTROY_BATCH_FWD_RESP 0x54UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_DESTROY_BATCH_FWD_RESP 0x55UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_ALL_BATCH_FWD_RESP_CMPL 0x5aUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_DRV_RGTR 0x64UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_DRV_RGTR_CMPL 0x65UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_DRV_UNRGTR 0x66UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_DRV_UNRGTR_CMPL 0x67UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_BUF_RGTR 0x68UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_BUF_RGTR_CMPL 0x69UL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_BUF_UNRGTR 0x6aUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_BUF_UNRGTR_CMPL 0x6bUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_MPC_TEST_CMD 0xcaUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_MPC_TEST_CMPL 0xcbUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_MPC_TEST_FWD_CMD 0xccUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_MPC_TEST_FWD_CMPL 0xcdUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_MPC_TEST_FWD_REQ 0xceUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_MPC_TEST_FWD_RESP 0xcfUL +#define MPC_CMD_HDR_REQ_SUB_TYPE_LAST MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_MPC_TEST_FWD_RESP + +#define MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_NONE 0x0UL +#define MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_BAD_TARGET_ID 0x1UL +#define MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_SA_NOT_INIT_ENABLED 0x2UL +#define MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_HW_CMD_FAILED 0x3UL +#define MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_BAD_PSP_MODE 0x4UL +#define MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_BAD_SPI 0x5UL +#define MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_SPI_THRESHOLD_BREACHED 0x6UL +#define MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_ACTIVE_QPS_EXIST 0x7UL +#define MPC_CMPL_HDR_ERROR_CODE_LAST MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_ACTIVE_QPS_EXIST + +/* mpc_cmpl_hdr (size:64b/8B) */ +struct mpc_cmpl_hdr { + u8 cmpl_type_reserved; + #define CMPL_TYPE_RESERVED_CMPL_TYPE_MASK 0x3fUL + #define CMPL_TYPE_RESERVED_CMPL_TYPE_SFT 0 + #define CMPL_TYPE_RESERVED_CMPL_TYPE_MPC_CMP_SHORT 0x1eUL + #define CMPL_TYPE_RESERVED_CMPL_TYPE_MPC_CMP_LONG 0x1fUL + #define CMPL_TYPE_RESERVED_CMPL_TYPE_LAST CMPL_TYPE_RESERVED_CMPL_TYPE_MPC_CMP_LONG + u8 error_code_mp_client; + #define ERROR_CODE_MP_CLIENT_ERROR_CODE_MASK 0xfUL + #define ERROR_CODE_MP_CLIENT_ERROR_CODE_SFT 0 + #define ERROR_CODE_MP_CLIENT_MP_CLIENT_MASK 0xf0UL + #define ERROR_CODE_MP_CLIENT_MP_CLIENT_SFT 4 + u8 req_type; + u8 req_subtype; + __le32 opaque; +}; + #endif /* _BNGE_HSI_H_ */ -- 2.43.5