Update the FDT generation for the per-CPU PPI timers to be GICv5-compatible. In order to keep the code working for both older GICs and GICv5, we introduce an offset for GICv5. This effectively applies the implicit shift that is applied to PPI IDs on older GICs (they follow the SGIs) explicitly. Signed-off-by: Sascha Bischoff --- arm64/timer.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arm64/timer.c b/arm64/timer.c index 2ac6144f..0945510d 100644 --- a/arm64/timer.c +++ b/arm64/timer.c @@ -12,13 +12,22 @@ void timer__generate_fdt_nodes(void *fdt, struct kvm *kvm) int irqs[5] = {13, 14, 11, 10, 12}; int nr = ARRAY_SIZE(irqs); u32 irq_prop[nr * 3]; + u32 type, offset; if (!kvm->cfg.arch.nested_virt) nr--; + if (kvm->cfg.arch.irqchip == IRQCHIP_GICV5) { + type = GICV5_FDT_IRQ_TYPE_PPI; + offset = 16; + } else { + type = GIC_FDT_IRQ_TYPE_PPI; + offset = 0; + } + for (int i = 0; i < nr; i++) { - irq_prop[i * 3 + 0] = cpu_to_fdt32(GIC_FDT_IRQ_TYPE_PPI); - irq_prop[i * 3 + 1] = cpu_to_fdt32(irqs[i]); + irq_prop[i * 3 + 0] = cpu_to_fdt32(type); + irq_prop[i * 3 + 1] = cpu_to_fdt32(irqs[i] + offset); irq_prop[i * 3 + 2] = cpu_to_fdt32(cpu_mask | IRQ_TYPE_LEVEL_LOW); } -- 2.34.1