Add the Samsung S3NRN4V NCI NFC controller on i2c1. Its XI clock comes from the PMK7635 CLK7_LN buffer (RPMH_LN_BB_CLK2), and the reference is load-bearing: with no clocks reference at all the chip polls but never activates a tag, while a held rpmh clock vote lets it read (verified on hardware). PVDD is fed from PM7550 LDO20, the rail the downstream driver switches for this chip. The enable line is routed to the chip's power-down input. The driver drives its "en" descriptor to logical 1 to hold the chip powered down, and on this board the chip is off while the pin is physically high, so the line is GPIO_ACTIVE_HIGH. The pin is pulled up so the chip stays off while the line is not driven. Assisted-by: Claude:claude-opus-4-8 Assisted-by: Claude:claude-fable-5 Signed-off-by: Jorijn van der Graaf --- .../boot/dts/qcom/milos-fairphone-fp6.dts | 33 +++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts index ebdca0e2d2f3..bdba848275db 100644 --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts @@ -601,9 +601,22 @@ &gcc { }; &i2c1 { - /* Samsung NFC @ 0x27 */ - status = "okay"; + + nfc@27 { + compatible = "samsung,s3nrn4v"; + reg = <0x27>; + + interrupts-extended = <&tlmm 31 IRQ_TYPE_EDGE_RISING>; + en-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; + + pvdd-supply = <&vreg_l20b>; + + pinctrl-0 = <&nfc_default>; + pinctrl-names = "default"; + }; }; &i2c3 { @@ -825,6 +838,22 @@ &tlmm { <13 1>, /* NC */ <63 2>; /* WLAN UART */ + nfc_default: nfc-default-state { + irq-pins { + pins = "gpio31"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pd-pins { + pins = "gpio56"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + sdc2_card_det_n: sdc2-card-det-state { pins = "gpio65"; function = "gpio"; -- 2.55.0