The C45 accessors were setting the GR (register number) field twice, once with the 16-bit register address truncated to five bits, and then overwritten with the C45 devad. This is harmless since the field was being cleared prior to being updated with the C45 devad, except for the extra work. Remove the redundant code. Signed-off-by: Russell King (Oracle) --- Untested, as I don't have my Jetson Xavier NX platform with me (and probably won't do for a few weeks.) While this patch has been prepared on top of "net: stmmac: mdio: use netdev_priv() directly" it shouldn't conflict if that patch is not applied before this one. drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c index 86021e6b67b2..da4542be756a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c @@ -311,12 +311,10 @@ static int stmmac_mdio_read_c45(struct mii_bus *bus, int phyaddr, int devad, value |= (phyaddr << priv->hw->mii.addr_shift) & priv->hw->mii.addr_mask; - value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) & priv->hw->mii.clk_csr_mask; value |= MII_GMAC4_READ; value |= MII_GMAC4_C45E; - value &= ~priv->hw->mii.reg_mask; value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT; @@ -409,14 +407,12 @@ static int stmmac_mdio_write_c45(struct mii_bus *bus, int phyaddr, value |= (phyaddr << priv->hw->mii.addr_shift) & priv->hw->mii.addr_mask; - value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) & priv->hw->mii.clk_csr_mask; value |= MII_GMAC4_WRITE; value |= MII_GMAC4_C45E; - value &= ~priv->hw->mii.reg_mask; value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT; -- 2.47.2