Populate selected PEBS feature names in FEAT_PERF_CAPABILITIES to make the corresponding bits user-visible CPU feature knobs, allowing them to be explicitly enabled or disabled via -cpu +/-. Once named, these bits become part of the guest CPU configuration contract. If a VM is configured with such a feature enabled, migration to a destination that does not support the feature may fail, as the destination cannot honor the guest-visible CPU model. The PEBS_FMT bits are not exposed, as target/i386 currently does not support multi-bit CPU properties. Co-developed-by: Dapeng Mi Signed-off-by: Dapeng Mi Signed-off-by: Zide Chen --- V2: - Add the missing comma after "pebs-arch-reg". - Simplify the PEBS_FMT description in the commit message. target/i386/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d3e9d3c40b0a..f2c83b4f259c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1618,10 +1618,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .type = MSR_FEATURE_WORD, .feat_names = { NULL, NULL, NULL, NULL, + NULL, NULL, "pebs-trap", "pebs-arch-reg", NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, "full-width-write", NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, "full-width-write", "pebs-baseline", NULL, + NULL, "pebs-timing-info", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, -- 2.52.0