ice_ptp_calc_deskew_eth56g() ignores the return value of read_poll_timeout(). If register reads succeed but the DESKEW valid bit never appears, the timeout is treated as success. If a register read fails, the poll condition can also inspect deskew_i before a successful read and continue polling instead of stopping on the hard error. The function then returns an int error through its u32 deskew return type. Return the deskew value through an output parameter. Stop polling when either the read fails or the valid bit appears, then propagate the register error or the poll timeout separately before calculating and applying the deskew value. Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products") Assisted-by: Codex:gpt-5 Signed-off-by: Pengpeng Hou --- Changes since v2: https://lore.kernel.org/all/20260706144325.91320-1-pengpeng@iscas.ac.cn/ - capture and propagate the read_poll_timeout() result - stop the poll immediately on a register read error - initialize deskew_i before it is used by the poll condition - do not carry the v2 Reviewed-by because the poll logic changed drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 42 ++++++++++++++++++---------- 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 8e5f97835954..76ee71400163 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -1736,24 +1736,30 @@ static u32 ice_ptp_calc_bitslip_eth56g(struct ice_hw *hw, u8 port, u32 bs, * @ds: deskew multiplier * @rs: RS-FEC enabled * @spd: link speed + * @deskew: output parameter for the calculated deskew value * - * Return: calculated deskew value + * Return: 0 on success, negative error code otherwise */ -static u32 ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds, - bool rs, enum ice_eth56g_link_spd spd) +static int ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds, + bool rs, enum ice_eth56g_link_spd spd, + u32 *deskew) { - u32 deskew_i, deskew_f; - int err; + u32 deskew_i = 0, deskew_f; + int err, ret; - if (!ds) + if (!ds) { + *deskew = 0; return 0; + } - read_poll_timeout(ice_read_ptp_reg_eth56g, err, - FIELD_GET(PHY_REG_DESKEW_0_VALID, deskew_i), 500, - 50 * USEC_PER_MSEC, false, hw, port, PHY_REG_DESKEW_0, - &deskew_i); + ret = read_poll_timeout(ice_read_ptp_reg_eth56g, err, + err || FIELD_GET(PHY_REG_DESKEW_0_VALID, deskew_i), + 500, 50 * USEC_PER_MSEC, false, hw, port, + PHY_REG_DESKEW_0, &deskew_i); if (err) return err; + if (ret) + return ret; deskew_f = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL_FRAC, deskew_i); deskew_i = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL, deskew_i); @@ -1766,7 +1772,9 @@ static u32 ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds, deskew_i = FIELD_PREP(ICE_ETH56G_MAC_CFG_RX_OFFSET_INT, deskew_i); /* Shift 3 fractional bits to the end of the integer part */ deskew_f <<= ICE_ETH56G_MAC_CFG_FRAC_W - PHY_REG_DESKEW_0_RLEVEL_FRAC_W; - return mul_u32_u32_fx_q9(deskew_i | deskew_f, ds); + *deskew = mul_u32_u32_fx_q9(deskew_i | deskew_f, ds); + + return 0; } /** @@ -1789,6 +1797,7 @@ static int ice_phy_set_offsets_eth56g(struct ice_hw *hw, u8 port, { u32 rx_offset, tx_offset, bs_ds; bool onestep, sfd; + int err; onestep = hw->ptp.phy.eth56g.onestep_ena; sfd = hw->ptp.phy.eth56g.sfd_ena; @@ -1805,11 +1814,16 @@ static int ice_phy_set_offsets_eth56g(struct ice_hw *hw, u8 port, if (sfd) rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.sfd); - if (spd < ICE_ETH56G_LNK_SPD_40G) + if (spd < ICE_ETH56G_LNK_SPD_40G) { bs_ds = ice_ptp_calc_bitslip_eth56g(hw, port, bs_ds, fc, rs, spd); - else - bs_ds = ice_ptp_calc_deskew_eth56g(hw, port, bs_ds, rs, spd); + } else { + err = ice_ptp_calc_deskew_eth56g(hw, port, bs_ds, rs, spd, + &bs_ds); + if (err) + return err; + } + rx_offset = add_u32_u32_fx(rx_offset, bs_ds); rx_offset &= ICE_ETH56G_MAC_CFG_RX_OFFSET_INT | ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC; -- 2.50.1 (Apple Git-155)