Add support for the GigaDevice GD25B512 512Mbit (64 MiB) SPI NOR flash. The chip exposes valid JESD216B SFDP tables including 4-byte address instruction tables, from which geometry and opcodes are discovered. Stateless 4-byte opcodes and status register locking are enabled. Read, write, and erase functionality across the full memory array have been tested on hardware. Cc: stable@vger.kernel.org # v6.1+ Co-developed-by: Adam Calabrigo Signed-off-by: Adam Calabrigo Signed-off-by: Matthew Parker --- drivers/mtd/spi-nor/gigadevice.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c index 6a2e6ebda148..de96cefde516 100644 --- a/drivers/mtd/spi-nor/gigadevice.c +++ b/drivers/mtd/spi-nor/gigadevice.c @@ -64,6 +64,10 @@ static const struct flash_info gigadevice_nor_parts[] = { .id = SNOR_ID(0xc8, 0x40, 0x19), .name = "gd25q256", .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6, + }, { + .id = SNOR_ID(0xc8, 0x47, 0x1a), + .flags = SPI_NOR_HAS_LOCK, + .fixup_flags = SPI_NOR_4B_OPCODES, }, { .id = SNOR_ID(0xc8, 0x60, 0x16), .name = "gd25lq32", -- 2.51.0