When inspecting the config space of a Connect-X physical function in an s390 system after it was initialized by the mlx5_core device driver, we found the function to be enabled to request AtomicOps despite the system's root-complex lacking support for completing them: 1ed0:00:00.1 Ethernet controller: Mellanox Technologies MT2894 Family [ConnectX-6 Lx] Subsystem: Mellanox Technologies Device 0002 [...] DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- AtomicOpsCtl: ReqEn+ IDOReq- IDOCompl- LTR- EmergencyPowerReductionReq- 10BitTagReq- OBFF Disabled, EETLPPrefixBlk- Turns out the device driver calls pci_enable_atomic_ops_to_root() which defaulted to enable AtomicOps requests even if it had no information about the root-port that the PCIe device is attached to. Similarly, AtomicOps requests are enabled for root-complex integrated endpoints (RCiEPs) unconditionally. Change the logic of pci_enable_atomic_ops_to_root() to fully traverse the PCIe tree upwards, check that the bridge devices support delivering AtomicOps transactions, and finally check that there is a root-port at the end that does support completing AtomicOps - or that the support for completing AtomicOps at the root complex is announced through some other arch-specific way. This announcement is implemented through the new pcibios_connects_to_atomicops_capable_rc() function - with a default implementation to always return "true" to leave the semantics for RCiEPs intact. For s390, override pcibios_connects_to_atomicops_capable_rc() to always return "false". Do not change the enablement of AtomicOps requests if there is no positive confirmation that the root complex can complete PCIe AtomicOps. Reported-by: Alexander Schmidt Cc: stable@vger.kernel.org Fixes: 430a23689dea ("PCI: Add pci_enable_atomic_ops_to_root()") Signed-off-by: Gerd Bayer --- arch/s390/pci/pci.c | 5 +++++ drivers/pci/pci.c | 46 +++++++++++++++++++++++++++++----------------- include/linux/pci.h | 1 + 3 files changed, 35 insertions(+), 17 deletions(-) diff --git a/arch/s390/pci/pci.c b/arch/s390/pci/pci.c index 2a430722cbe415dd56c92fed2e513e524f46481a..a13235d3218e8ca451e25fe8d9094500fa21aa26 100644 --- a/arch/s390/pci/pci.c +++ b/arch/s390/pci/pci.c @@ -265,6 +265,11 @@ static int zpci_cfg_store(struct zpci_dev *zdev, int offset, u32 val, u8 len) return rc; } +bool pcibios_connects_to_atomicops_capable_rc(struct pci_dev *pdev, u32 cap_mask) +{ + return false; +} + resource_size_t pcibios_align_resource(void *data, const struct resource *res, resource_size_t size, resource_size_t align) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 8479c2e1f74f1044416281aba11bf071ea89488a..c1143f8e6b2a0f029feb3c4390ac6f33837f6de1 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3660,6 +3660,21 @@ void pci_acs_init(struct pci_dev *dev) pci_disable_broken_acs_cap(dev); } + +static bool pci_is_atomicops_capable_rp(struct pci_dev *dev, u32 cap, u32 cap_mask) +{ + if ((!dev) || + !(pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)) + return false; + + return ((cap & cap_mask) == cap_mask); +} + +bool __weak pcibios_connects_to_atomicops_capable_rc(struct pci_dev *pdev, u32 cap_mask) +{ + return true; +} + /** * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port * @dev: the PCI device @@ -3676,7 +3691,7 @@ void pci_acs_init(struct pci_dev *dev) int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) { struct pci_bus *bus = dev->bus; - struct pci_dev *bridge; + struct pci_dev *bridge = NULL; u32 cap, ctl2; /* @@ -3714,29 +3729,26 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) switch (pci_pcie_type(bridge)) { /* Ensure switch ports support AtomicOp routing */ case PCI_EXP_TYPE_UPSTREAM: - case PCI_EXP_TYPE_DOWNSTREAM: - if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) - return -EINVAL; - break; - - /* Ensure root port supports all the sizes we care about */ - case PCI_EXP_TYPE_ROOT_PORT: - if ((cap & cap_mask) != cap_mask) - return -EINVAL; - break; - } - - /* Ensure upstream ports don't block AtomicOps on egress */ - if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) { + /* Upstream ports must not block AtomicOps on egress */ pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl2); if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) return -EINVAL; + fallthrough; + /* All switch ports need to route AtomicOps */ + case PCI_EXP_TYPE_DOWNSTREAM: + if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) + return -EINVAL; + break; } - bus = bus->parent; } + /* Finally, last bridge must be root port and support requested sizes */ + if (!(pci_is_atomicops_capable_rp(bridge, cap, cap_mask) || + pcibios_connects_to_atomicops_capable_rc(dev, cap_mask))) + return -EINVAL; + pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_ATOMIC_REQ); return 0; @@ -3813,7 +3825,7 @@ static int __pci_request_region(struct pci_dev *pdev, int bar, err_out: pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar, - &pdev->resource[bar]); + &pdev->resource[bar]); return -EBUSY; } diff --git a/include/linux/pci.h b/include/linux/pci.h index 1c270f1d512301de4d462fe7e5097c32af5c6f8d..498f266c9838c55e9b03d03fef49a82358047f4f 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -692,6 +692,7 @@ void pci_set_host_bridge_release(struct pci_host_bridge *bridge, void *release_data); int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); +bool pcibios_connects_to_atomicops_capable_rc(struct pci_dev *pdev, u32 cap_mask); #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ -- 2.51.0