Microchip LAN969x has DWC3 compatible controller, though limited to 2.0(HS) speed, so document it. Signed-off-by: Robert Marko --- Changes in v2: * Fix example indentation .../bindings/usb/microchip,lan9691-dwc3.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/microchip,lan9691-dwc3.yaml diff --git a/Documentation/devicetree/bindings/usb/microchip,lan9691-dwc3.yaml b/Documentation/devicetree/bindings/usb/microchip,lan9691-dwc3.yaml new file mode 100644 index 000000000000..6b49ef0a6bdd --- /dev/null +++ b/Documentation/devicetree/bindings/usb/microchip,lan9691-dwc3.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/microchip,lan9691-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip LAN969x SuperSpeed DWC3 USB SoC controller + +maintainers: + - Robert Marko + +select: + properties: + compatible: + contains: + enum: + - microchip,lan9691-dwc3 + required: + - compatible + +properties: + compatible: + items: + - enum: + - microchip,lan9691-dwc3 + - const: snps,dwc3 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Gated USB DRD clock + - description: Controller reference clock + + clock-names: + items: + - const: bus_early + - const: ref + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +allOf: + - $ref: snps,dwc3.yaml# + +examples: + - | + #include + #include + + usb@300000 { + compatible = "microchip,lan9691-dwc3", "snps,dwc3"; + reg = <0x300000 0x80000>; + interrupts = ; + clocks = <&clks GCK_GATE_USB_DRD>, + <&clks GCK_ID_USB_REFCLK>; + clock-names = "bus_early", "ref"; + }; -- 2.52.0