Add PDM XO4 divider clocks and make the PDM XO4 branches propagate rate requests to them on QCS615, QCS8300, SA8775P, and SC7280. This lets GP_MND select the supported PDM source clock rates. Signed-off-by: Taniya Das --- drivers/clk/qcom/gcc-qcs615.c | 20 ++++++++++++++++++++ drivers/clk/qcom/gcc-qcs8300.c | 20 ++++++++++++++++++++ drivers/clk/qcom/gcc-sa8775p.c | 20 ++++++++++++++++++++ drivers/clk/qcom/gcc-sc7280.c | 20 ++++++++++++++++++++ 4 files changed, 80 insertions(+) diff --git a/drivers/clk/qcom/gcc-qcs615.c b/drivers/clk/qcom/gcc-qcs615.c index e096af7d82bf558bedf524eb2ca959f3e9e5c22e..9b558ea023ad62e6d465155e21c54376d7b99732 100644 --- a/drivers/clk/qcom/gcc-qcs615.c +++ b/drivers/clk/qcom/gcc-qcs615.c @@ -1654,6 +1654,20 @@ static struct clk_branch gcc_pdm_ahb_clk = { }, }; +static struct clk_regmap_div gcc_pdm_xo4_div_clk_src = { + .reg = 0x33028, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pdm_xo4_div_clk_src", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +}; + static struct clk_branch gcc_pdm_xo4_clk = { .halt_reg = 0x33008, .halt_check = BRANCH_HALT, @@ -1662,6 +1676,11 @@ static struct clk_branch gcc_pdm_xo4_clk = { .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data) { .name = "gcc_pdm_xo4_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pdm_xo4_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2802,6 +2821,7 @@ static struct clk_regmap *gcc_qcs615_clocks[] = { [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, + [GCC_PDM_XO4_DIV_CLK_SRC] = &gcc_pdm_xo4_div_clk_src.clkr, [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, diff --git a/drivers/clk/qcom/gcc-qcs8300.c b/drivers/clk/qcom/gcc-qcs8300.c index 916617a001c854c1a0349c1793a427a2822acfab..4a152e95aa997bdcc7ec56a6ae96c61b3575cd88 100644 --- a/drivers/clk/qcom/gcc-qcs8300.c +++ b/drivers/clk/qcom/gcc-qcs8300.c @@ -2280,6 +2280,20 @@ static struct clk_branch gcc_pdm_ahb_clk = { }, }; +static struct clk_regmap_div gcc_pdm_xo4_div_clk_src = { + .reg = 0x3f028, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pdm_xo4_div_clk_src", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +}; + static struct clk_branch gcc_pdm_xo4_clk = { .halt_reg = 0x3f008, .halt_check = BRANCH_HALT, @@ -2288,6 +2302,11 @@ static struct clk_branch gcc_pdm_xo4_clk = { .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data) { .name = "gcc_pdm_xo4_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pdm_xo4_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -3501,6 +3520,7 @@ static struct clk_regmap *gcc_qcs8300_clocks[] = { [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, + [GCC_PDM_XO4_DIV_CLK_SRC] = &gcc_pdm_xo4_div_clk_src.clkr, [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c index 0e02af686614162dd7d5d9ab9f3a20c390ed0512..5ed3ec74b210807813f97120a4a19773f3f67d0d 100644 --- a/drivers/clk/qcom/gcc-sa8775p.c +++ b/drivers/clk/qcom/gcc-sa8775p.c @@ -2712,6 +2712,20 @@ static struct clk_branch gcc_pdm_ahb_clk = { }, }; +static struct clk_regmap_div gcc_pdm_xo4_div_clk_src = { + .reg = 0x3f028, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pdm_xo4_div_clk_src", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +}; + static struct clk_branch gcc_pdm_xo4_clk = { .halt_reg = 0x3f008, .halt_check = BRANCH_HALT, @@ -2720,6 +2734,11 @@ static struct clk_branch gcc_pdm_xo4_clk = { .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data){ .name = "gcc_pdm_xo4_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pdm_xo4_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -4406,6 +4425,7 @@ static struct clk_regmap *gcc_sa8775p_clocks[] = { [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, + [GCC_PDM_XO4_DIV_CLK_SRC] = &gcc_pdm_xo4_div_clk_src.clkr, [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, [GCC_QMIP_DISP1_AHB_CLK] = &gcc_qmip_disp1_ahb_clk.clkr, diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index 78399993cdcee225d2f21f39844b056193bdfca3..dc7a855be0234f6135d461175099862f2d486d9a 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -1913,6 +1913,20 @@ static struct clk_branch gcc_pdm_ahb_clk = { }, }; +static struct clk_regmap_div gcc_pdm_xo4_div_clk_src = { + .reg = 0x33028, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pdm_xo4_div_clk_src", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +}; + static struct clk_branch gcc_pdm_xo4_clk = { .halt_reg = 0x33008, .halt_check = BRANCH_HALT, @@ -1921,6 +1935,11 @@ static struct clk_branch gcc_pdm_xo4_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm_xo4_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_pdm_xo4_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -3250,6 +3269,7 @@ static struct clk_regmap *gcc_sc7280_clocks[] = { [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, + [GCC_PDM_XO4_DIV_CLK_SRC] = &gcc_pdm_xo4_div_clk_src.clkr, [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, -- 2.34.1