The RK3328 GMAC clock delay macros define enable/disable controls for TX and RX clock delay. While the TX definitions are correct, the RXCLK_DLY_DISABLE macro incorrectly clears bit 0. The macros RK3328_GMAC_TXCLK_DLY_DISABLE and RK3328_GMAC_RXCLK_DLY_DISABLE are not referenced anywhere in the driver code. Remove them to clean up unused definitions. No functional change. Signed-off-by: Alok Tiwari --- drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c index f6687c2f30f6..9e9ae8525720 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c @@ -557,9 +557,7 @@ static const struct rk_gmac_ops rk3308_ops = { #define RK3328_GMAC_RMII_MODE GRF_BIT(9) #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) -#define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) -#define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0) /* RK3328_GRF_MACPHY_CON1 */ #define RK3328_MACPHY_RMII_MODE GRF_BIT(9) -- 2.50.1